Simulation Results: otp_ctrl

 
20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.39 %
  • code
  • 86.21 %
  • assert
  • 95.52 %
  • func
  • 92.45 %
  • line
  • 90.40 %
  • branch
  • 86.94 %
  • cond
  • 94.05 %
  • toggle
  • 96.12 %
  • FSM
  • 63.54 %
Validation stages
V1
88.46%
V2
97.21%
V2S
97.12%
V3
22.77%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.890s 105.848us 1 1 100.00
smoke 10 10 100.00
otp_ctrl_smoke 8.410s 1101.354us 10 10 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.670s 1081.844us 1 1 100.00
csr_rw 5 5 100.00
otp_ctrl_csr_rw 2.020s 578.594us 5 5 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 9.550s 2238.515us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 5.210s 188.630us 1 1 100.00
csr_mem_rw_with_rand_reset 2 5 40.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.360s 145.862us 2 5 40.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otp_ctrl_csr_rw 2.020s 578.594us 5 5 100.00
otp_ctrl_csr_aliasing 5.210s 188.630us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.330s 51.102us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.720s 48.673us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 21.010s 13509.857us 1 1 100.00
init_fail 300 300 100.00
otp_ctrl_init_fail 7.820s 2411.040us 300 300 100.00
partition_check 46 60 76.67
otp_ctrl_background_chks 32.900s 2470.350us 10 10 100.00
otp_ctrl_check_fail 105.120s 19552.535us 36 50 72.00
regwen_during_otp_init 30 30 100.00
otp_ctrl_regwen 19.590s 5193.935us 30 30 100.00
partition_lock 30 30 100.00
otp_ctrl_dai_lock 44.120s 17140.565us 30 30 100.00
interface_key_check 10 10 100.00
otp_ctrl_parallel_key_req 30.920s 2207.250us 10 10 100.00
lc_interactions 210 210 100.00
otp_ctrl_parallel_lc_req 22.600s 12088.512us 10 10 100.00
otp_ctrl_parallel_lc_esc 41.540s 19166.982us 200 200 100.00
otp_dai_errors 23 25 92.00
otp_ctrl_dai_errs 37.780s 5243.784us 23 25 92.00
otp_macro_errors 5 10 50.00
otp_ctrl_macro_errs 65.760s 37905.551us 5 10 50.00
test_access 10 10 100.00
otp_ctrl_test_access 45.520s 27062.288us 10 10 100.00
stress_all 10 10 100.00
otp_ctrl_stress_all 465.150s 60579.694us 10 10 100.00
intr_test 10 10 100.00
otp_ctrl_intr_test 1.920s 156.284us 10 10 100.00
alert_test 10 10 100.00
otp_ctrl_alert_test 2.630s 870.249us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otp_ctrl_tl_errors 6.010s 713.812us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otp_ctrl_tl_errors 6.010s 713.812us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.670s 1081.844us 1 1 100.00
otp_ctrl_csr_rw 2.020s 578.594us 5 5 100.00
otp_ctrl_csr_aliasing 5.210s 188.630us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.460s 117.179us 5 5 100.00
tl_d_partial_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.670s 1081.844us 1 1 100.00
otp_ctrl_csr_rw 2.020s 578.594us 5 5 100.00
otp_ctrl_csr_aliasing 5.210s 188.630us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.460s 117.179us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
tl_intg_err 30 30 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
otp_ctrl_tl_intg_err 29.660s 20117.190us 25 25 100.00
prim_count_check 5 5 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
prim_fsm_check 5 5 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
otp_ctrl_tl_intg_err 29.660s 20117.190us 25 25 100.00
sec_cm_secret_mem_scramble 10 10 100.00
otp_ctrl_smoke 8.410s 1101.354us 10 10 100.00
sec_cm_part_mem_digest 10 10 100.00
otp_ctrl_smoke 8.410s 1101.354us 10 10 100.00
sec_cm_dai_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
sec_cm_kdi_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
sec_cm_lci_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
sec_cm_part_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
sec_cm_scrmbl_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
sec_cm_timer_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
sec_cm_dai_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
sec_cm_kdi_seed_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
sec_cm_kdi_entropy_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
sec_cm_lci_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
sec_cm_part_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
sec_cm_scrmbl_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
sec_cm_timer_integ_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
sec_cm_timer_cnsty_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
sec_cm_timer_lfsr_redun 5 5 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
sec_cm_dai_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 41.540s 19166.982us 200 200 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
sec_cm_lci_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 41.540s 19166.982us 200 200 100.00
sec_cm_kdi_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 41.540s 19166.982us 200 200 100.00
sec_cm_part_fsm_local_esc 205 210 97.62
otp_ctrl_parallel_lc_esc 41.540s 19166.982us 200 200 100.00
otp_ctrl_macro_errs 65.760s 37905.551us 5 10 50.00
sec_cm_scrmbl_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 41.540s 19166.982us 200 200 100.00
sec_cm_timer_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 41.540s 19166.982us 200 200 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
sec_cm_dai_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 41.540s 19166.982us 200 200 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
sec_cm_lci_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 41.540s 19166.982us 200 200 100.00
sec_cm_kdi_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 41.540s 19166.982us 200 200 100.00
sec_cm_part_fsm_global_esc 205 210 97.62
otp_ctrl_parallel_lc_esc 41.540s 19166.982us 200 200 100.00
otp_ctrl_macro_errs 65.760s 37905.551us 5 10 50.00
sec_cm_scrmbl_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 41.540s 19166.982us 200 200 100.00
sec_cm_timer_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 41.540s 19166.982us 200 200 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
sec_cm_part_data_reg_integrity 300 300 100.00
otp_ctrl_init_fail 7.820s 2411.040us 300 300 100.00
sec_cm_part_data_reg_bkgn_chk 36 50 72.00
otp_ctrl_check_fail 105.120s 19552.535us 36 50 72.00
sec_cm_part_mem_regren 30 30 100.00
otp_ctrl_dai_lock 44.120s 17140.565us 30 30 100.00
sec_cm_part_mem_sw_unreadable 30 30 100.00
otp_ctrl_dai_lock 44.120s 17140.565us 30 30 100.00
sec_cm_part_mem_sw_unwritable 30 30 100.00
otp_ctrl_dai_lock 44.120s 17140.565us 30 30 100.00
sec_cm_lc_part_mem_sw_noaccess 30 30 100.00
otp_ctrl_dai_lock 44.120s 17140.565us 30 30 100.00
sec_cm_access_ctrl_mubi 30 30 100.00
otp_ctrl_dai_lock 44.120s 17140.565us 30 30 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
otp_ctrl_smoke 8.410s 1101.354us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 30 30 100.00
otp_ctrl_dai_lock 44.120s 17140.565us 30 30 100.00
sec_cm_test_bus_lc_gated 10 10 100.00
otp_ctrl_smoke 8.410s 1101.354us 10 10 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 153.280s 43449.239us 5 5 100.00
sec_cm_direct_access_config_regwen 30 30 100.00
otp_ctrl_regwen 19.590s 5193.935us 30 30 100.00
sec_cm_check_trigger_config_regwen 10 10 100.00
otp_ctrl_smoke 8.410s 1101.354us 10 10 100.00
sec_cm_check_config_regwen 10 10 100.00
otp_ctrl_smoke 8.410s 1101.354us 10 10 100.00
sec_cm_macro_mem_integrity 5 10 50.00
otp_ctrl_macro_errs 65.760s 37905.551us 5 10 50.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 14.370s 7969.001us 1 1 100.00
stress_all_with_rand_reset 22 100 22.00
otp_ctrl_stress_all_with_rand_reset 124.140s 10399.876us 22 100 22.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 38 test runs
otp_ctrl_check_fail 62742105852045757203014619324231343018393734398100942430103182470022772658723 13869
UVM_INFO @ 5335728776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 31872509355957535020040435160701741611083437998800720954743092667204152921241 3445
UVM_INFO @ 2637179857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 9324964806950955077987897590772729352965004466190836073649284946756771660349 403
UVM_INFO @ 795769124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 34825782400003299969225476400403957822493171850504511780839180836529371780648 5233
UVM_INFO @ 8481514030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 47865979957557192839074718487246362685963290655475321731707135001932545598989 1012
UVM_INFO @ 288931893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 6144511334763538611799379590708228418320164675060396113815270229194029932215 2288
UVM_INFO @ 171091372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 82991859092446234476033723665766343549321057085608116885621924330551926196187 9785
UVM_INFO @ 22559779637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 31609503936476581362582563079244726825071870789651190021344529296224805036849 147
UVM_INFO @ 62560581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 49324887243498532543059563621764008439171136829133694989991181964019721444680 2812
UVM_INFO @ 4629583799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 58147204931558446998231780011279036326420313335199268379353652677487022432040 3555
UVM_INFO @ 1204296903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 26487719410637173354356035334271621003252183201064553950458643703852085001872 15517
UVM_INFO @ 2309724868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 77595296868501007633626898962110424698360239069160557114996574037427132157753 7310
UVM_INFO @ 7866132036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 67532016791244277872775674426246489229199195904729774222399308337852609070300 10495
UVM_INFO @ 1511835732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 56862175330595949589987602942212141481084040621975375245204284523997148697627 1863
UVM_INFO @ 2822741217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 26430154224838534022012037615384176551438856137230233431932635752813994853348 189
UVM_INFO @ 126643295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 22850853693655178673739706162730842867165467188761657647821491393059849819697 8442
UVM_INFO @ 31091776794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76728901625617990824075415849609544713578173381456046541235761429998699796968 1948
UVM_INFO @ 392244907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 53929389928572824867150575334603888324114376152877484106823730416314779863175 8748
UVM_INFO @ 1454972783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 50639319260493714014388310691724054974689577030826411536493162491560808722929 1495
UVM_INFO @ 209178605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 19655792988635299020234421272649250663433603290163645037781406445167502330016 12560
UVM_INFO @ 6155131100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 52728819971108701217558536360894789862876734345095609014791541373664330624050 297
UVM_INFO @ 4738390911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 90954872007926157925197721019305400845648042644392582288724152387050328048996 12748
UVM_INFO @ 9361742927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 106778322181322005671641435758594345579631928545290407551499840767288957956251 5441
UVM_INFO @ 957891903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50232855942992542071553342230513240735516121476050486197358201489503651572983 5761
UVM_INFO @ 4082324302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 96895912351794614597427053999191074797780092740551237591208583169031980019085 14901
UVM_INFO @ 22446387031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 19723294749324741805788005785724263494259528172666923360795249159537102648266 2556
UVM_INFO @ 482039822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 47388338967241301984495768364974509573068701122508495508651428889701623761620 1855
UVM_INFO @ 544271926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23738165862734214273429022709709217483351330555412270214974549742647539128343 2142
UVM_INFO @ 1055085172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 54600441309110082425084907954027439961869514263461982464179245099118584251656 5443
UVM_INFO @ 1374590245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18638213267091521560301377653969454229356603218259975811221933153265282262144 17570
UVM_INFO @ 39447626252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 92417089500336722849421157779927999927426058773494517932849857731992201533761 1913
UVM_INFO @ 259538413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 10733643080053162840716147788701191395382058737368428830535114275908544418157 40187
UVM_INFO @ 3703439076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50280466129873391190379778312541112387477809547322959869876463233625652788466 149
UVM_INFO @ 61329570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 109253560741941136343317711366233035509615943926386604800983231653481892619781 3283
UVM_INFO @ 3672782529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73864911765399302413419877118050451854538023440009871142391529310630670232306 15610
UVM_INFO @ 1897570112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 33946200551205281630965280078267794760688535643937668291230804617827042159564 10417
UVM_INFO @ 609502758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 81337935669221349922763131875910681237508654558392033704319071168477754570108 14723
UVM_INFO @ 737258126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 95289390119573419517664284894383964411457114117930599775801384873374291309512 251
UVM_INFO @ 135415076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 28 test runs
otp_ctrl_csr_mem_rw_with_rand_reset 103966276117649751438645831198974549881984387422009104789536449979207698136214 98
UVM_INFO @ 62564982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 111602456791992047532502514878441320275079629998131775064441159109584659046300 92
UVM_INFO @ 34839931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4222516952541785676978014242732548226901893835989796056687310724794496492173 92
UVM_INFO @ 52188379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 54880728141834487852847812210831572040332898648650504042292582255548560810881 137
UVM_INFO @ 606756803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 86904260844263861957480113714052506128050529750181009805815108926269706635224 7010
UVM_INFO @ 12601569441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 37710264640217991258825617612705750146355385822381762790144454849306617120639 92
UVM_INFO @ 53180048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 97451948683627790060294366610799691277539896695573543839988994140487700476079 92
UVM_INFO @ 51895857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 92353705994659719422678835284324299862822458269897172181612224502194413973099 93
UVM_INFO @ 52832279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 8459407058220557449438783286921437952922413092865994748008975531649352506485 33340
UVM_INFO @ 9547104243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 26738896065933027610835894022602081017692052419345510227937152729363103189978 7907
UVM_INFO @ 1464623589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 36614371872319887588982869380534087452341188925915160252353732940252912770948 93
UVM_INFO @ 107246328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 105447198563256665481928515323450442389812539657819527126561323321855702775073 682
UVM_INFO @ 153158419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 58661329740096049560285832591559750281462449932785660399003595875931351103688 18817
UVM_INFO @ 3990924408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18780263168643718757800493440699991025805228057325633637701309754321227472084 178
UVM_INFO @ 908376152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114766779912609181463071795806244858736142673064532916289592813350702987704786 136
UVM_INFO @ 197200027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 94222849352446356040452606504170865930836980361623311726257970902280402061235 144
UVM_INFO @ 6778807574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 106360771847252165999600813547699355531391081719867766194878529255873461227817 92
UVM_INFO @ 106741532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 33492247808616290564705810099098080786804774794073304965319085487471490884738 4568
UVM_INFO @ 6000307762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 100013571131574103673650805827158189892388512775192283015375599498967346120607 37074
UVM_INFO @ 10114727992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76888232988520419670316566833965641209807283620472918483102302845635318585080 3432
UVM_INFO @ 8572220213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 106224113886210328192640640968738227610488339902160270187511234330693202743658 189
UVM_INFO @ 523214311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 81127147916028521411418390889138302961992793473329711099950419133894973833425 4976
UVM_INFO @ 24524108228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 61262620384916435018666415391690974060669820912069768223791081324345479467965 9527
UVM_INFO @ 2405526638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 44750663957590550461891363352442259318238610280685169589985439306607511966014 67543
UVM_INFO @ 3995571123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 48857776292415310039483741849369311678932326438883306197042610895480317788423 148
UVM_INFO @ 60284406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 17932292480001589864157521277444185462546780762603676355905413490229973323453 12571
UVM_INFO @ 5048661259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 109329010263572374192451217747238333711978934279401324483304309837770936798576 312
UVM_INFO @ 1041056593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 5095488783283285718052853255810727601955927977324448215848512860277199044118 4414
UVM_INFO @ 1435729019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 15 test runs
otp_ctrl_stress_all_with_rand_reset 90732462161594891720180551378032582288093513916602572964351899081157709042920 2542
UVM_INFO @ 377174790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 54767532142432221703648586460881816588770464066386171437529116082590332860885 433
UVM_INFO @ 625161152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 54979586967762788496864631862589498602047021295491040619573349115522522244011 5525
UVM_INFO @ 3160460708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 44236858398257681057963536720449266298919014199805875344628138186704456974925 177
UVM_INFO @ 155417813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 40420563656106281002050669407155673774821598562946463242451428447734977700276 17525
UVM_INFO @ 12981447554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 85209184486658756958736312163745482038239178406229696279670470989236365526579 3962
UVM_INFO @ 27179797384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 52324861376771198783049343962333257140473139774864528551795806692799993714971 501
UVM_INFO @ 87144087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80679047390405286509791287380090017066187611865120199120530940356948775322847 15401
UVM_INFO @ 33915859820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 5214863262188833258058411651932630086118834896474400263228963804722633706769 6063
UVM_INFO @ 155728824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 81765268872425753121356619123690244786426009026357501039796219636921783104893 11318
UVM_INFO @ 22459609740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 103817757850361946586811935260498571693388404176195111905330666342387769735543 1017
UVM_INFO @ 497547771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2381172358838069216956114530405072097967822353406361404903710592814871661391 125
UVM_INFO @ 63854308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 78770731881833218231924830644358953922636147692122247826625905242621012157455 1909
UVM_INFO @ 14652476873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 33867076213687549094641893504723949573917317721623548920200766756097228365006 5045
UVM_INFO @ 15590024842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 60977480108374981241215582150658846985054631864838564266547596123922303903463 1680
UVM_INFO @ 1483903139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 13 test runs
otp_ctrl_csr_mem_rw_with_rand_reset 109516121669831452991804031260845325721302054617320424092531361365125223298469 92
UVM_INFO @ 26412843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 22729252140136864070534367271398380045084575101572507105743203058482251413606 92
UVM_INFO @ 103772392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 91421252832853487217763956733405416647491907629613357566484412576873604394281 330
UVM_INFO @ 3228267821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 5267737258209568512234068719447432307650198018615498778597924134296035012113 12184
UVM_INFO @ 1438571102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 22309234538130179889596828107293496706547846261878605502465375583980302755097 3236
UVM_INFO @ 122199936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35962790115008927149872136942705305979141849210007005155767372056800872113925 12894
UVM_INFO @ 5947617355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 106329502676385743717833894148437882444863190689970010205613624878311329611324 7829
UVM_INFO @ 13729012061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 32089502548139033729172608563726952228091902853762537006781227208668592109591 8042
UVM_INFO @ 3796380028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42665479662042097274905776042269078465975005615961283892219859410767015190106 24562
UVM_INFO @ 2430220667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 34640321340267170623264608180703780073278798434531043153896010506622507753225 1409
UVM_INFO @ 1252471404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 110624680423857363527849021255655661821427115256583793927989583429562239375495 47195
UVM_INFO @ 30807285999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 95211281484432458749188292943171008100072620360823487881101365130426368570877 92
UVM_INFO @ 73096838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 51845739062178016494511375118067386489308135414504793745541297027223794551338 1573
UVM_INFO @ 5408533654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen 3 test runs
otp_ctrl_stress_all_with_rand_reset 75927125431681481816371581853430742666221697618362474092098815084384605420691 5683
UVM_INFO @ 2451694827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42826368181321977762328312145914329354905412256413214466818219881127793691622 10813
UVM_INFO @ 9252588893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 26129995033078529194007311763102629930383613041683211336906561832128077413156 3900
UVM_INFO @ 1061808124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) 2 test runs
otp_ctrl_stress_all_with_rand_reset 42960152420460019051296713497358653881790976185735798186348737695199992176694 3801
UVM_INFO @ 163280709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 90594262081518018662144502005103844683796268651383636238645442339964661653599 52550
UVM_INFO @ 5154294944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otp_ctrl_stress_all_with_rand_reset 44309617450510789631206540992240343880006724740665748866410164494094335209823 27101
UVM_INFO @ 45640507127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed 1 test run
otp_ctrl_stress_all_with_rand_reset 104346218968819358289929041488444102422475852880540058198408361345196037729488 786
UVM_INFO @ 144674919 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 144685020 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 144967848 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 144988050 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
Offending '(cio_test_en_o == *)' 1 test run
otp_ctrl_stress_all_with_rand_reset 62010874133970206028432475482691374589059419717770816603011908875673009569168 465
UVM_ERROR @ 301780898 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 301780898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---