Simulation Results: pwrmgr

 
20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.41 %
  • code
  • 97.54 %
  • assert
  • 98.69 %
  • func
  • 99.01 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 96.61 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
92.70%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
pwrmgr_smoke 0.980s 25.590us 10 10 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 1.050s 34.183us 1 1 100.00
csr_rw 5 5 100.00
pwrmgr_csr_rw 0.930s 22.867us 5 5 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.990s 2119.013us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.220s 52.950us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.160s 110.267us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
pwrmgr_csr_rw 0.930s 22.867us 5 5 100.00
pwrmgr_csr_aliasing 1.220s 52.950us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 10 10 100.00
pwrmgr_wakeup 1.560s 304.070us 10 10 100.00
control_clks 10 10 100.00
pwrmgr_wakeup 1.560s 304.070us 10 10 100.00
aborted_low_power 20 20 100.00
pwrmgr_aborted_low_power 1.260s 105.706us 10 10 100.00
pwrmgr_lowpower_invalid 1.000s 43.293us 10 10 100.00
reset 15 20 75.00
pwrmgr_reset 2.300s 1000.000us 6 10 60.00
pwrmgr_reset_invalid 1.280s 112.122us 9 10 90.00
main_power_glitch_reset 6 10 60.00
pwrmgr_reset 2.300s 1000.000us 6 10 60.00
reset_wakeup_race 10 10 100.00
pwrmgr_wakeup_reset 1.250s 309.904us 10 10 100.00
lowpower_wakeup_race 10 10 100.00
pwrmgr_lowpower_wakeup_race 1.170s 81.180us 10 10 100.00
disable_rom_integrity_check 8 10 80.00
pwrmgr_disable_rom_integrity_check 1.370s 140.166us 8 10 80.00
stress_all 7 10 70.00
pwrmgr_stress_all 15.850s 10308.853us 7 10 70.00
intr_test 10 10 100.00
pwrmgr_intr_test 0.960s 21.434us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
pwrmgr_tl_errors 2.680s 411.350us 25 25 100.00
tl_d_illegal_access 25 25 100.00
pwrmgr_tl_errors 2.680s 411.350us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
pwrmgr_csr_hw_reset 1.050s 34.183us 1 1 100.00
pwrmgr_csr_rw 0.930s 22.867us 5 5 100.00
pwrmgr_csr_aliasing 1.220s 52.950us 1 1 100.00
pwrmgr_same_csr_outstanding 1.070s 19.659us 5 5 100.00
tl_d_partial_access 12 12 100.00
pwrmgr_csr_hw_reset 1.050s 34.183us 1 1 100.00
pwrmgr_csr_rw 0.930s 22.867us 5 5 100.00
pwrmgr_csr_aliasing 1.220s 52.950us 1 1 100.00
pwrmgr_same_csr_outstanding 1.070s 19.659us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
pwrmgr_tl_intg_err 2.290s 4086.276us 25 25 100.00
pwrmgr_sec_cm 1.660s 394.555us 5 5 100.00
prim_count_check 5 5 100.00
pwrmgr_sec_cm 1.660s 394.555us 5 5 100.00
prim_fsm_check 5 5 100.00
pwrmgr_sec_cm 1.660s 394.555us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
pwrmgr_tl_intg_err 2.290s 4086.276us 25 25 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.450s 730.900us 10 10 100.00
sec_cm_rom_ctrl_intersig_mubi 20 20 100.00
pwrmgr_wakeup_reset 1.250s 309.904us 10 10 100.00
pwrmgr_repeat_wakeup_reset 2.540s 837.083us 10 10 100.00
sec_cm_rstmgr_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.210s 56.635us 10 10 100.00
sec_cm_esc_rx_clk_bkgn_chk 10 10 100.00
pwrmgr_esc_clk_rst_malfunc 0.980s 30.844us 10 10 100.00
sec_cm_esc_rx_clk_local_esc 5 5 100.00
pwrmgr_sec_cm 1.660s 394.555us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
pwrmgr_sec_cm 1.660s 394.555us 5 5 100.00
sec_cm_fsm_terminal 5 5 100.00
pwrmgr_sec_cm 1.660s 394.555us 5 5 100.00
sec_cm_ctrl_flow_global_esc 10 10 100.00
pwrmgr_global_esc 0.860s 28.619us 10 10 100.00
sec_cm_main_pd_rst_local_esc 10 10 100.00
pwrmgr_glitch 0.950s 27.515us 10 10 100.00
sec_cm_ctrl_config_regwen 10 10 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.640s 272.947us 10 10 100.00
sec_cm_wakeup_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.930s 22.867us 5 5 100.00
sec_cm_reset_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.930s 22.867us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 7 10 70.00
pwrmgr_escalation_timeout 0.980s 356.230us 7 10 70.00
stress_all_with_rand_reset 9 10 90.00
pwrmgr_stress_all_with_rand_reset 11.640s 12638.458us 9 10 90.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 6 test runs
pwrmgr_reset 51459073637807701187732211287531552396195161292108376359519219362054890048752 99
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 94679324684626603176399869124473043272011626555081429935947131966070549918037 121
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_reset 98784395129784637465320316877966789031643994468610723625856000040145108787625 162
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_reset 24304072505177855073708074358565317282575210931529102900764985928583402294740 76
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_reset 100489065819829142757681701666755294728795556433895126038414906425705155248902 110
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 79957588535893574793840247509442192007420424441530720051549424942355465995286 88
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)' 3 test runs
pwrmgr_escalation_timeout 29382977628526495995880287636833249515471677752997861324099060966396544007704 79
UVM_ERROR @ 356229619 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 356229619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 27477665216060846125064182937331788424323143078810547863073781437360528501057 79
UVM_ERROR @ 100385303 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 100385303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 98420805575541132254539618165792505530547530519712283922165532400883507757711 79
UVM_ERROR @ 101812097 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 101812097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 3 test runs
pwrmgr_stress_all 12341457899243502184840286065094678546338215817539610667078007565910516792241 1050
UVM_INFO @ 12340203217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 22890028195604792715211549060406121748637959918675775909816282478614766541021 284
UVM_INFO @ 10308853058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 88799108408393459108469718410734641775274287317781021742023223795824875679880 119
UVM_INFO @ 10040892939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitReleaseLcRst 1 test run
pwrmgr_reset_invalid 70647349809874576373171915174366696133876331641416361887889460599874860945937 86
UVM_INFO @ 85389050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_base_vseq.sv:607) [pwrmgr_common_vseq] timeout waiting for pwrmgr fast fsm target activity 1 test run
pwrmgr_stress_all_with_rand_reset 25706946971362547368994096743716633120423102155781046111731708829408174211837 2327
UVM_INFO @ 3480731497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---