Simulation Results: rom_ctrl/32kb

 
20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.52 %
  • code
  • 98.68 %
  • assert
  • 97.82 %
  • func
  • 99.05 %
  • line
  • 99.46 %
  • branch
  • 100.00 %
  • cond
  • 98.37 %
  • toggle
  • 95.57 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
94.92%
V3
95.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 7.180s 183.734us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.460s 927.669us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 5.430s 123.609us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.430s 557.325us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 293.887us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.980s 609.955us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 5.430s 123.609us 5 5 100.00
rom_ctrl_csr_aliasing 4.000s 293.887us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.230s 171.370us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.050s 127.042us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 4.540s 137.404us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 27.190s 1130.586us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 9.030s 566.177us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 7.450s 8283.046us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 11.130s 377.347us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 11.130s 377.347us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 4.460s 927.669us 1 1 100.00
rom_ctrl_csr_rw 5.430s 123.609us 5 5 100.00
rom_ctrl_csr_aliasing 4.000s 293.887us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.500s 176.296us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 4.460s 927.669us 1 1 100.00
rom_ctrl_csr_rw 5.430s 123.609us 5 5 100.00
rom_ctrl_csr_aliasing 4.000s 293.887us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.500s 176.296us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 109.350s 13784.941us 17 20 85.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.540s 5178.801us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 270.800s 6874.499us 5 5 100.00
rom_ctrl_tl_intg_err 70.130s 438.071us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 270.800s 6874.499us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 270.800s 6874.499us 5 5 100.00
sec_cm_checker_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 109.350s 13784.941us 17 20 85.00
sec_cm_checker_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 109.350s 13784.941us 17 20 85.00
sec_cm_checker_fsm_local_esc 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 109.350s 13784.941us 17 20 85.00
sec_cm_compare_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 109.350s 13784.941us 17 20 85.00
sec_cm_compare_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 109.350s 13784.941us 17 20 85.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 270.800s 6874.499us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 270.800s 6874.499us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 7.180s 183.734us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 7.180s 183.734us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 7.180s 183.734us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 70.130s 438.071us 25 25 100.00
sec_cm_bus_local_esc 19 22 86.36
rom_ctrl_corrupt_sig_fatal_chk 109.350s 13784.941us 17 20 85.00
rom_ctrl_kmac_err_chk 9.030s 566.177us 2 2 100.00
sec_cm_mux_mubi 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 109.350s 13784.941us 17 20 85.00
sec_cm_mux_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 109.350s 13784.941us 17 20 85.00
sec_cm_ctrl_redun 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 109.350s 13784.941us 17 20 85.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.540s 5178.801us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 270.800s 6874.499us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 19 20 95.00
rom_ctrl_stress_all_with_rand_reset 487.950s 9635.330us 19 20 95.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 3 test runs
rom_ctrl_corrupt_sig_fatal_chk 94543767794438613892352413552286168545305834928415955905004877462436106471065 108
UVM_INFO @ 2139131983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 63856621057621367973961920888754701908642965256779766576527689013337065862269 78
UVM_INFO @ 172492682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 26059093296179430745303189695883215920251361377991575650611234675194356938191 98
UVM_INFO @ 2160741428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 100837440509776966263498585325111801719783421972993757086383028475206367122928 79
UVM_INFO @ 137404149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 33099209389507805027599646948664583094948002561393504925723738697098560091357 79
UVM_INFO @ 170041048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:235) [scoreboard] Check failed item.d_data[i**+:*] == exp_data[i**+:*] (* [*] vs * [*]) TLUL ROM read data incorrect 1 test run
rom_ctrl_stress_all_with_rand_reset 36878307400803861281761967997273681509594005898591909472111250792238605831599 101
UVM_INFO @ 943295768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---