Simulation Results: rom_ctrl/64kb

 
20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.47 %
  • code
  • 98.68 %
  • assert
  • 97.68 %
  • func
  • 99.05 %
  • line
  • 99.46 %
  • branch
  • 100.00 %
  • cond
  • 98.37 %
  • toggle
  • 95.57 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
100.00%
V3
95.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 12.030s 571.816us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 12.700s 2131.373us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 8.140s 287.674us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 9.440s 299.281us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 9.220s 2785.694us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 12.600s 534.136us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 8.140s 287.674us 5 5 100.00
rom_ctrl_csr_aliasing 9.220s 2785.694us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.590s 1069.371us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 10.200s 1216.616us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 11.690s 4283.230us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 70.360s 17943.439us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 18.690s 391.089us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 10.750s 298.231us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 16.270s 555.033us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 16.270s 555.033us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 12.700s 2131.373us 1 1 100.00
rom_ctrl_csr_rw 8.140s 287.674us 5 5 100.00
rom_ctrl_csr_aliasing 9.220s 2785.694us 1 1 100.00
rom_ctrl_same_csr_outstanding 11.530s 2925.054us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 12.700s 2131.373us 1 1 100.00
rom_ctrl_csr_rw 8.140s 287.674us 5 5 100.00
rom_ctrl_csr_aliasing 9.220s 2785.694us 1 1 100.00
rom_ctrl_same_csr_outstanding 11.530s 2925.054us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 227.750s 59950.478us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 48.930s 5878.979us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 618.590s 2196.369us 5 5 100.00
rom_ctrl_tl_intg_err 150.430s 461.262us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 618.590s 2196.369us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 618.590s 2196.369us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 227.750s 59950.478us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 227.750s 59950.478us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 227.750s 59950.478us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 227.750s 59950.478us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 227.750s 59950.478us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 618.590s 2196.369us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 618.590s 2196.369us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 12.030s 571.816us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 12.030s 571.816us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 12.030s 571.816us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 150.430s 461.262us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 227.750s 59950.478us 20 20 100.00
rom_ctrl_kmac_err_chk 18.690s 391.089us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 227.750s 59950.478us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 227.750s 59950.478us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 227.750s 59950.478us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 48.930s 5878.979us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 618.590s 2196.369us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 19 20 95.00
rom_ctrl_stress_all_with_rand_reset 440.570s 22919.595us 19 20 95.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 11032159470054757886032372275262042916250656448551206315689009969119351226464 79
UVM_INFO @ 170658190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 74542300278297432614957680934177483488882014627780986606073226197258765588014 79
UVM_INFO @ 4283229552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:235) [scoreboard] Check failed item.d_data[i**+:*] == exp_data[i**+:*] (* [*] vs * [*]) TLUL ROM read data incorrect 1 test run
rom_ctrl_stress_all_with_rand_reset 10833987025983746914778667455005457593720460136440187216810056365967638935378 93
UVM_INFO @ 1924104216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---