Simulation Results: rstmgr

 
20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.12 %
  • code
  • 99.66 %
  • assert
  • 98.93 %
  • func
  • 98.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.31 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.57%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
rstmgr_smoke 1.740s 289.816us 5 5 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.040s 147.161us 1 1 100.00
csr_rw 5 5 100.00
rstmgr_csr_rw 1.200s 93.483us 5 5 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 9.090s 2841.629us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.020s 227.000us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.480s 134.828us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rstmgr_csr_rw 1.200s 93.483us 5 5 100.00
rstmgr_csr_aliasing 2.020s 227.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 5 5 100.00
rstmgr_por_stretcher 1.250s 178.568us 5 5 100.00
sw_rst 5 5 100.00
rstmgr_sw_rst 3.350s 504.582us 5 5 100.00
sw_rst_reset_race 5 5 100.00
rstmgr_sw_rst_reset_race 1.690s 186.618us 5 5 100.00
reset_info 5 5 100.00
rstmgr_reset 7.890s 2220.334us 5 5 100.00
cpu_info 5 5 100.00
rstmgr_reset 7.890s 2220.334us 5 5 100.00
alert_info 5 5 100.00
rstmgr_reset 7.890s 2220.334us 5 5 100.00
reset_info_capture 5 5 100.00
rstmgr_reset 7.890s 2220.334us 5 5 100.00
stress_all 5 5 100.00
rstmgr_stress_all 51.220s 18205.758us 5 5 100.00
alert_test 10 10 100.00
rstmgr_alert_test 1.270s 92.568us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rstmgr_tl_errors 4.440s 568.368us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rstmgr_tl_errors 4.440s 568.368us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rstmgr_csr_hw_reset 1.040s 147.161us 1 1 100.00
rstmgr_csr_rw 1.200s 93.483us 5 5 100.00
rstmgr_csr_aliasing 2.020s 227.000us 1 1 100.00
rstmgr_same_csr_outstanding 2.200s 276.073us 5 5 100.00
tl_d_partial_access 12 12 100.00
rstmgr_csr_hw_reset 1.040s 147.161us 1 1 100.00
rstmgr_csr_rw 1.200s 93.483us 5 5 100.00
rstmgr_csr_aliasing 2.020s 227.000us 1 1 100.00
rstmgr_same_csr_outstanding 2.200s 276.073us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rstmgr_sec_cm 25.890s 16821.882us 5 5 100.00
rstmgr_tl_intg_err 4.250s 956.165us 25 25 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 25.890s 16821.882us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 25.890s 16821.882us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
rstmgr_tl_intg_err 4.250s 956.165us 25 25 100.00
sec_cm_scan_intersig_mubi 5 5 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.620s 182.076us 5 5 100.00
sec_cm_leaf_rst_bkgn_chk 24 25 96.00
rstmgr_leaf_rst_cnsty 12.980s 2814.640us 24 25 96.00
sec_cm_leaf_rst_shadow 5 5 100.00
rstmgr_leaf_rst_shadow_attack 1.640s 302.076us 5 5 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 25.890s 16821.882us 5 5 100.00
sec_cm_sw_rst_config_regwen 5 5 100.00
rstmgr_csr_rw 1.200s 93.483us 5 5 100.00
sec_cm_dump_ctrl_config_regwen 5 5 100.00
rstmgr_csr_rw 1.200s 93.483us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_cnsty_fault did not trigger max_delay:* 1 test run
rstmgr_leaf_rst_cnsty 25230221444524887887092492111484842494633860187653967966631445323538006431455 208
UVM_INFO @ 1079842963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---