Simulation Results: rstmgr_cnsty_chk

 
20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.52 %
  • code
  • 95.05 %
  • assert
  • 100.00 %
  • line
  • 98.41 %
  • branch
  • 98.31 %
  • cond
  • 86.21 %
  • toggle
  • 100.00 %
  • FSM
  • 92.31 %
Validation stages
unmapped
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 8 10 80.00
rstmgr_cnsty_chk_test 4.350s 10619.522us 8 10 80.00

Error Messages

   Test seed line log context
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *)) 2 test runs
rstmgr_cnsty_chk_test 76242786895479247632752561376512368459760247278135090258423803972233627682454 175
UVM_INFO @ 1896462119 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16
UVM_INFO @ 1915342119 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16
UVM_INFO @ 1934222119 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16
UVM_INFO @ 1953102119 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16
rstmgr_cnsty_chk_test 54899385195217936706363736318232374641192654322594478679358143272528063158061 175
UVM_INFO @ 2040725155 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16
UVM_INFO @ 2061045155 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16
UVM_INFO @ 2081365155 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16
UVM_INFO @ 2101685155 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16