| V1 |
|
100.00% |
| V2 |
|
85.04% |
| V2S |
|
100.00% |
| V3 |
|
37.50% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 1.870s | 162.085us | 20 | 20 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.900s | 86.483us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| rv_timer_csr_rw | 0.890s | 115.791us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_timer_csr_bit_bash | 1.660s | 156.713us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_timer_csr_aliasing | 1.110s | 54.914us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.820s | 127.779us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| rv_timer_csr_rw | 0.890s | 115.791us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.110s | 54.914us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 1 | 20 | 5.00 | |||
| rv_timer_random_reset | 1.620s | 604.998us | 1 | 20 | 5.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 2.470s | 3055.073us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 818.780s | 2951436.377us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 818.780s | 2951436.377us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 6.370s | 4784.735us | 20 | 20 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| rv_timer_alert_test | 0.870s | 17.260us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| rv_timer_intr_test | 0.830s | 18.014us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 2.890s | 187.612us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 2.890s | 187.612us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.900s | 86.483us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.890s | 115.791us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.110s | 54.914us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.960s | 37.866us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.900s | 86.483us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.890s | 115.791us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.110s | 54.914us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.960s | 37.866us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| rv_timer_sec_cm | 1.150s | 113.171us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.730s | 518.374us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| rv_timer_tl_intg_err | 1.730s | 518.374us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 2 | 10 | 20.00 | |||
| rv_timer_min | 1.000s | 102.050us | 2 | 10 | 20.00 | |
| max_value | 1 | 10 | 10.00 | |||
| rv_timer_max | 1.840s | 149.294us | 1 | 10 | 10.00 | |
| stress_all_with_rand_reset | 12 | 20 | 60.00 | |||
| rv_timer_stress_all_with_rand_reset | 49.280s | 25623.590us | 12 | 20 | 60.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | 27 test runs | |||
| rv_timer_min | 67284828070850879742559850862003052144845537495094116387600380789527277317479 | 77 |
UVM_INFO @ 251866262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 66490339747265209884279104697814206733950782186160236755966250165570794641710 | 75 |
UVM_INFO @ 604998327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 111397041348332457105286911209274742531760408825319105367050070781147871183512 | 76 |
UVM_INFO @ 586764915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 107782283535303606699336971699733093744978436941816558433746926646949334190682 | 76 |
UVM_INFO @ 70212468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 87903522780038854802157541751775961604158551993614618527659364861958979520426 | 76 |
UVM_INFO @ 372895717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 109654816670505074315945434528434328184236420187271418964466947971561419965720 | 75 |
UVM_INFO @ 464648755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 17862112120012269853327231863969508457424602274340493445019936326351709627676 | 75 |
UVM_INFO @ 300374268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 55196838318946570251515987856867626914414706085153542050098713850276578180199 | 75 |
UVM_INFO @ 400474059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 2408407041641009187643686264463781783623027058213387124384899726994343420371 | 75 |
UVM_INFO @ 746359379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 41286921466320464835582631641866850061716733917204125039007091027851749550068 | 75 |
UVM_INFO @ 126604445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 72821747641437638679621343250298269675297957332349708322137386544789858135894 | 75 |
UVM_INFO @ 157063263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 2882454295117984662121056665681069904908660594796897332930741896337933271624 | 76 |
UVM_INFO @ 61410093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 27436286245088922030365710642429242060763099028110807319522025988044949939137 | 76 |
UVM_INFO @ 904515883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 22392599959202676396112883684467121043796204535051589168824302284477687587074 | 75 |
UVM_INFO @ 102049782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 30279281322501762786163147452490343022493324674663618024760101882608120110457 | 76 |
UVM_INFO @ 945367336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 56327959065680100327296939866380994553301080484198768598885087767067783279371 | 75 |
UVM_INFO @ 103812506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 106583044448289277641841020432182138506018948264215327512442889775925158028527 | 75 |
UVM_INFO @ 152314755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 19836694374087882583168776246158623656619742318418631144533977784898565040209 | 75 |
UVM_INFO @ 108273841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 34993513452183349515862749552099204518433346662089390233518898700055101630945 | 75 |
UVM_INFO @ 990796872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 57248136281202422907300626696862037830731932521258468345959529891109479123551 | 75 |
UVM_INFO @ 60576197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 106147293394488563759412038026571035569266028820373670802475957317976720335537 | 77 |
UVM_INFO @ 774849390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 23297699290192951265936822654801168115086308292616390750379114425534702500325 | 75 |
UVM_INFO @ 278165509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 57578229513955961787153209530736367403492109908484954008697375142741565550164 | 76 |
UVM_INFO @ 654876133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 676430894236312857426563867351162890402854586093960402160247893203369013650 | 75 |
UVM_INFO @ 311899261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 30388869460125343782011336730477076734652014311798266147966525957848257359462 | 75 |
UVM_INFO @ 216396456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 114297005080810684211503564337457106166206799672417790149623371851935307003388 | 75 |
UVM_INFO @ 123087353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 57522592911525461483067595921513818552715091206003254115351828998729591845163 | 77 |
UVM_INFO @ 174401653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 9 test runs | |||
| rv_timer_max | 56105269186638202149304552073248447106806714077802472258711619860879226753929 | 75 |
UVM_INFO @ 45155366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 71107173190016100659705321187218025092892225929874007483427455799313366452430 | 75 |
UVM_INFO @ 43098156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 16957407625217313078273605529436583507260362468055796210440797607363836211734 | 75 |
UVM_INFO @ 93094346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 111446014012320594100504930613639960718196305091334089207940843328829900838006 | 75 |
UVM_INFO @ 475816081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 67058878703743046856277075638574575647806232683945743280016462178768618858443 | 75 |
UVM_INFO @ 44794307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 50062457250744917228297574037446163732765453744072687744513355393012947140394 | 75 |
UVM_INFO @ 379752531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 60740035013336318536596517087711948530289434476699915871803509527222808904151 | 75 |
UVM_INFO @ 149294250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 98912789059140218225874189252143900935333307984698668794534912692576769162804 | 75 |
UVM_INFO @ 84372698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 2625140347051867848121859044731756524152056181717918767806027002448344115562 | 75 |
UVM_INFO @ 90852477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) | 7 test runs | |||
| rv_timer_stress_all_with_rand_reset | 109513013296872261926707897126895726276701188071854446810091074418209696961342 | 84 |
UVM_INFO @ 298289231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 88884053600800061070220650744298619882800607947128447131385595754847404095797 | 116 |
UVM_INFO @ 18274814314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 44360024174029144878959390939535923333811464504778731368420146794988051464027 | 188 |
UVM_INFO @ 2386537186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 106931982845373706038685550725009098840819051857511313514355773236846255334785 | 186 |
UVM_INFO @ 1364918902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 99431311889760755767355789406872612512705283738702699836784025067465409704493 | 149 |
UVM_INFO @ 819161221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 80994134814108741996527030590253270146389518076306008457215987114047758227553 | 134 |
UVM_INFO @ 2538167400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 78575283471453197590605057891415188495943505419250310083239950894431875426131 | 325 |
UVM_INFO @ 4725251227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | 1 test run | |||
| rv_timer_stress_all_with_rand_reset | 62966071568464087956009321645544412138800412617624489904766877863916796378500 | 145 |
UVM_INFO @ 7322897524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|