Simulation Results: spi_host

 
20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.57 %
  • code
  • 91.30 %
  • assert
  • 95.65 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.35%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 76.000s 3088.772us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 3.000s 17.884us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 29.829us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 5.000s 133.580us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 5.000s 142.987us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 4.000s 54.189us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 29.829us 5 5 100.00
spi_host_csr_aliasing 5.000s 142.987us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 17.670us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 58.363us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 22.295us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 17.000s 1017.956us 10 10 100.00
spi_host_error_cmd 2.000s 43.396us 10 10 100.00
spi_host_event 96.000s 25779.771us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 4.000s 205.009us 10 10 100.00
speed 10 10 100.00
spi_host_speed 4.000s 205.009us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 4.000s 205.009us 10 10 100.00
upper_range_clkdiv 4 5 80.00
spi_host_upper_range_clkdiv 1537.000s 185021.754us 4 5 80.00
sw_reset 10 10 100.00
spi_host_sw_reset 210.000s 8102.690us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 101.372us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 4.000s 205.009us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 4.000s 205.009us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 76.000s 3088.772us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 76.000s 3088.772us 10 10 100.00
stress_all 9 10 90.00
spi_host_stress_all 44.000s 11985.857us 9 10 90.00
spien 10 10 100.00
spi_host_spien 103.000s 28146.969us 10 10 100.00
stall 9 10 90.00
spi_host_status_stall 1132.000s 1000000.000us 9 10 90.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 30.000s 4673.943us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 17.000s 1017.956us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 4.000s 21.846us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 126.101us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 3.000s 47.207us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 3.000s 47.207us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 3.000s 17.884us 1 1 100.00
spi_host_csr_rw 2.000s 29.829us 5 5 100.00
spi_host_csr_aliasing 5.000s 142.987us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 39.653us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 3.000s 17.884us 1 1 100.00
spi_host_csr_rw 2.000s 29.829us 5 5 100.00
spi_host_csr_aliasing 5.000s 142.987us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 39.653us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 179.384us 25 25 100.00
spi_host_sec_cm 2.000s 282.003us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 179.384us 25 25 100.00

Error Messages

   Test seed line log context
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* 1 test run
spi_host_upper_range_clkdiv 64734412788670715973282678337343563888992505175445142001403331623278297674675 181
UVM_INFO @ 185021753798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* 1 test run
spi_host_stress_all 86236392512273723787533262840789414576103108418134230255151831224239018629862 369
UVM_INFO @ 11985857297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
spi_host_status_stall 8030562037498495978822998177350943145522256902983048165511506059160938422822 6634
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---