Simulation Results

Simulation Results: sram_ctrl/main

20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
96.85 %

code
95.85 %

assert
98.10 %

func
96.60 %

block
96.30 %

line
97.05 %

branch
94.50 %

toggle
91.84 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		84.91%
V2S		100.00%
V3		100.00%

37/37 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				8	8	100.00
	sram_ctrl_smoke	6.000s	687.461us	8	8	100.00
csr_hw_reset				1	1	100.00
	sram_ctrl_csr_hw_reset	2.000s	52.541us	1	1	100.00
csr_rw				5	5	100.00
	sram_ctrl_csr_rw	2.000s	21.672us	5	5	100.00
csr_bit_bash				1	1	100.00
	sram_ctrl_csr_bit_bash	3.000s	784.699us	1	1	100.00
csr_aliasing				1	1	100.00
	sram_ctrl_csr_aliasing	2.000s	64.070us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	sram_ctrl_csr_mem_rw_with_rand_reset	5.000s	1458.629us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	sram_ctrl_csr_rw	2.000s	21.672us	5	5	100.00
	sram_ctrl_csr_aliasing	2.000s	64.070us	1	1	100.00
mem_walk				8	8	100.00
	sram_ctrl_mem_walk	280.000s	53652.604us	8	8	100.00
mem_partial_access				8	8	100.00
	sram_ctrl_mem_partial_access	115.000s	10382.507us	8	8	100.00

135/159 passed

84.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
multiple_keys				8	8	100.00
	sram_ctrl_multiple_keys	47.000s	39224.770us	8	8	100.00
stress_pipeline				8	8	100.00
	sram_ctrl_stress_pipeline	341.000s	7112.111us	8	8	100.00
bijection				8	8	100.00
	sram_ctrl_bijection	205.000s	216889.273us	8	8	100.00
access_during_key_req				8	8	100.00
	sram_ctrl_access_during_key_req	137.000s	132928.659us	8	8	100.00
lc_escalation				8	8	100.00
	sram_ctrl_lc_escalation	70.000s	40968.233us	8	8	100.00
executable				8	8	100.00
	sram_ctrl_executable	53.000s	6832.931us	8	8	100.00
partial_access				16	16	100.00
	sram_ctrl_partial_access	7.000s	1310.409us	8	8	100.00
	sram_ctrl_partial_access_b2b	421.000s	27415.848us	8	8	100.00
max_throughput				0	24	0.00
	sram_ctrl_max_throughput	7.000s	1395.916us	0	8	0.00
	sram_ctrl_throughput_w_partial_write	6.000s	1693.641us	0	8	0.00
	sram_ctrl_throughput_w_readback	7.000s	6632.303us	0	8	0.00
regwen				8	8	100.00
	sram_ctrl_regwen	15.000s	861.971us	8	8	100.00
ram_cfg				8	8	100.00
	sram_ctrl_ram_cfg	4.000s	1409.066us	8	8	100.00
stress_all				8	8	100.00
	sram_ctrl_stress_all	393.000s	44363.831us	8	8	100.00
alert_test				10	10	100.00
	sram_ctrl_alert_test	2.000s	44.491us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	sram_ctrl_tl_errors	5.000s	239.314us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	sram_ctrl_tl_errors	5.000s	239.314us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	sram_ctrl_csr_hw_reset	2.000s	52.541us	1	1	100.00
	sram_ctrl_csr_rw	2.000s	21.672us	5	5	100.00
	sram_ctrl_csr_aliasing	2.000s	64.070us	1	1	100.00
	sram_ctrl_same_csr_outstanding	2.000s	125.996us	5	5	100.00
tl_d_partial_access				12	12	100.00
	sram_ctrl_csr_hw_reset	2.000s	52.541us	1	1	100.00
	sram_ctrl_csr_rw	2.000s	21.672us	5	5	100.00
	sram_ctrl_csr_aliasing	2.000s	64.070us	1	1	100.00
	sram_ctrl_same_csr_outstanding	2.000s	125.996us	5	5	100.00

V2S

88/88 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
passthru_mem_tl_intg_err				5	5	100.00
	sram_ctrl_passthru_mem_tl_intg_err	29.000s	14710.044us	5	5	100.00
tl_intg_err				30	30	100.00
	sram_ctrl_sec_cm	4.000s	1226.917us	5	5	100.00
	sram_ctrl_tl_intg_err	3.000s	1338.705us	25	25	100.00
prim_count_check				5	5	100.00
	sram_ctrl_sec_cm	4.000s	1226.917us	5	5	100.00
sec_cm_bus_integrity				25	25	100.00
	sram_ctrl_tl_intg_err	3.000s	1338.705us	25	25	100.00
sec_cm_ctrl_config_regwen				8	8	100.00
	sram_ctrl_regwen	15.000s	861.971us	8	8	100.00
sec_cm_readback_config_regwen				8	8	100.00
	sram_ctrl_regwen	15.000s	861.971us	8	8	100.00
sec_cm_exec_config_regwen				5	5	100.00
	sram_ctrl_csr_rw	2.000s	21.672us	5	5	100.00
sec_cm_exec_config_mubi				8	8	100.00
	sram_ctrl_executable	53.000s	6832.931us	8	8	100.00
sec_cm_exec_intersig_mubi				8	8	100.00
	sram_ctrl_executable	53.000s	6832.931us	8	8	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				8	8	100.00
	sram_ctrl_executable	53.000s	6832.931us	8	8	100.00
sec_cm_lc_escalate_en_intersig_mubi				8	8	100.00
	sram_ctrl_lc_escalation	70.000s	40968.233us	8	8	100.00
sec_cm_prim_ram_ctrl_mubi				8	8	100.00
	sram_ctrl_mubi_enc_err	7.000s	2669.116us	8	8	100.00
sec_cm_mem_integrity				5	5	100.00
	sram_ctrl_passthru_mem_tl_intg_err	29.000s	14710.044us	5	5	100.00
sec_cm_mem_readback				8	8	100.00
	sram_ctrl_readback_err	9.000s	6621.390us	8	8	100.00
sec_cm_mem_scramble				8	8	100.00
	sram_ctrl_smoke	6.000s	687.461us	8	8	100.00
sec_cm_addr_scramble				8	8	100.00
	sram_ctrl_smoke	6.000s	687.461us	8	8	100.00
sec_cm_instr_bus_lc_gated				8	8	100.00
	sram_ctrl_executable	53.000s	6832.931us	8	8	100.00
sec_cm_ram_tl_lc_gate_fsm_sparse				5	5	100.00
	sram_ctrl_sec_cm	4.000s	1226.917us	5	5	100.00
sec_cm_key_global_esc				8	8	100.00
	sram_ctrl_lc_escalation	70.000s	40968.233us	8	8	100.00
sec_cm_key_local_esc				5	5	100.00
	sram_ctrl_sec_cm	4.000s	1226.917us	5	5	100.00
sec_cm_init_ctr_redun				5	5	100.00
	sram_ctrl_sec_cm	4.000s	1226.917us	5	5	100.00
sec_cm_scramble_key_sideload				8	8	100.00
	sram_ctrl_smoke	6.000s	687.461us	8	8	100.00
sec_cm_tlul_fifo_ctr_redun				5	5	100.00
	sram_ctrl_sec_cm	4.000s	1226.917us	5	5	100.00

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				8	8	100.00
	sram_ctrl_stress_all_with_rand_reset	41.000s	2826.498us	8	8	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [] vs [*])				16 test runs
	sram_ctrl_max_throughput	25396835910059392950833025006119485119564514662875467360060990707296894494899	86	UVM_INFO @ 1395915984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_partial_write	39484920318099598048395962818899470870168243657232360677230014193196275451186	86	UVM_INFO @ 1553510816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_max_throughput	103202271635350731888225906770970854879443851016675248554794429459072962251023	86	UVM_INFO @ 687616486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_partial_write	54794088973909097396492385255446388229240133198950039358444794061675197434849	86	UVM_INFO @ 2640451265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_max_throughput	2159752185059682223281992921168972040953798508985979269689920065126320864784	86	UVM_INFO @ 2639012392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_partial_write	93723770968435481286178854981788530807674203468101558196218283825688246045834	86	UVM_INFO @ 13201618278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_max_throughput	11777506261882539307147685776625125956082202973482890826837904277971401933122	86	UVM_INFO @ 681689083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_partial_write	77892999105492242566818354254173890002743580842972975042788282455514636541413	86	UVM_INFO @ 1693641218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_max_throughput	73418061877420669352250380891988102983330453141933533215465091004490202958298	86	UVM_INFO @ 3877436320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_partial_write	87175099689474632009394039066919287344581217830647673408096418717589219595668	86	UVM_INFO @ 2871583321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_max_throughput	40568169228086348384998822206566591024233285299803730347380746734957919309689	86	UVM_INFO @ 1397497459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_partial_write	97814934063831691894897882840596535495387494926540063527241729419206436094	86	UVM_INFO @ 8250869551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_max_throughput	16789811236172468364373209704067569250093284102833686656094958434155824274076	86	UVM_INFO @ 686096090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_partial_write	25490779161714193424189195788548084117727346479087010526085501734472991501164	86	UVM_INFO @ 5969754636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_max_throughput	106171787109289434900797433738965328282951308621533634098054560418495661595015	86	UVM_INFO @ 680073430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_partial_write	61742860372366052946158550623454473813943490940205701736823650619277826417059	86	UVM_INFO @ 686418549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [] vs [*])				8 test runs
	sram_ctrl_throughput_w_readback	71606143610954304106562292268189592199167100851129704816034623503277685967753	86	UVM_INFO @ 4380642716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_readback	68983219374119345594735070599646774995906727566991586186150273887118763773072	86	UVM_INFO @ 6632303499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_readback	69375826022920341994083148759891085161569511245490890363162665403585595223516	86	UVM_INFO @ 1370353212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_readback	30030188045503573517799614353867706738083380932371072865299143997139221710083	86	UVM_INFO @ 657913595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_readback	1050760855207361825925488061195357886404992642264796464060542382212197297208	86	UVM_INFO @ 2655034934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_readback	24197555553889418048837815811160605429256629321200874557904727232995457359756	86	UVM_INFO @ 664535578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_readback	77860901659810035909370422373236648284323736191245039035804847570855969096340	86	UVM_INFO @ 665398499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_readback	31566926657630620653186576484582239748765465286126362612569068460826477359044	86	UVM_INFO @ 2292535653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---