Simulation Results: sram_ctrl/ret

 
20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.53 %
  • code
  • 82.50 %
  • assert
  • 98.08 %
  • func
  • 97.00 %
  • block
  • 94.03 %
  • line
  • 95.21 %
  • branch
  • 89.83 %
  • toggle
  • 78.31 %
  • FSM
  • 66.67 %
Validation stages
V1
97.30%
V2
84.91%
V2S
100.00%
V3
87.50%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 3.000s 252.446us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 14.038us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 34.999us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 212.449us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 17.234us 1 1 100.00
csr_mem_rw_with_rand_reset 4 5 80.00
sram_ctrl_csr_mem_rw_with_rand_reset 10.000s 10004.245us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 34.999us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 17.234us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 11.000s 3223.388us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 4.000s 99.754us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 17.000s 3541.608us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 246.000s 8780.242us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 11.000s 2300.833us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 21.000s 1077.817us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 7.000s 3060.197us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 16.000s 3999.349us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 2.000s 39.147us 8 8 100.00
sram_ctrl_partial_access_b2b 378.000s 26516.999us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 2.000s 29.245us 0 8 0.00
sram_ctrl_throughput_w_partial_write 2.000s 26.662us 0 8 0.00
sram_ctrl_throughput_w_readback 2.000s 128.507us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 16.000s 3082.129us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 2.000s 39.788us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 46.000s 6005.042us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 47.395us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 285.682us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 285.682us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 14.038us 1 1 100.00
sram_ctrl_csr_rw 2.000s 34.999us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 17.234us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 87.411us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 14.038us 1 1 100.00
sram_ctrl_csr_rw 2.000s 34.999us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 17.234us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 87.411us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 540.281us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 5.000s 4951.170us 5 5 100.00
sram_ctrl_tl_intg_err 3.000s 103.060us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 4951.170us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 3.000s 103.060us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 16.000s 3082.129us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 16.000s 3082.129us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 34.999us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 16.000s 3999.349us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 16.000s 3999.349us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 16.000s 3999.349us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 7.000s 3060.197us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 2.000s 312.127us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 540.281us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 2.000s 34.385us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 3.000s 252.446us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 3.000s 252.446us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 16.000s 3999.349us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 4951.170us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 7.000s 3060.197us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 4951.170us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 4951.170us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 3.000s 252.446us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 4951.170us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 8 87.50
sram_ctrl_stress_all_with_rand_reset 58.000s 4636.236us 7 8 87.50

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 113383548769706738941855864774282805449691044470246868804781168029532286139806 86
UVM_INFO @ 35774680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 106249349819310190383668595457412960746510214653697913268040895828853301790023 86
UVM_INFO @ 131749752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 89154055446986461673385141621592114746477549433176979919527505038526955091745 86
UVM_INFO @ 29244979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 7842628174456961142297406700021772924202898809416047219078105478090021615281 86
UVM_INFO @ 26661834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 41777259494179926078517381626306246832666863867927998952973603699202530980749 86
UVM_INFO @ 248067576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 2425987974159680154487485956321038297215835332551233950982178303684586278880 86
UVM_INFO @ 358399534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 86427733944761866983576930136925257224331111212450136929905623682601588968874 86
UVM_INFO @ 151163659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 82873263051024754414999553182271276110314403002440328300764270295666651309938 86
UVM_INFO @ 33295883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 30601856153846772791451884176148353909491339382168620410623577462253544173697 86
UVM_INFO @ 145876832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 105697768585580811570081812685605188539144190131457748439722663720871916433848 86
UVM_INFO @ 27850717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 54520215645910032877194009129098180362679391351130584504948172733714848091451 86
UVM_INFO @ 132077531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 39232661737422819348808704562770634483337749678101694378980489882143088666089 86
UVM_INFO @ 26535262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 1685730476735796752133641694930266121751893912384407391452879222728766909694 86
UVM_INFO @ 34953224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 4214309165957334126937761954478536686351083451231738989144542267562528206427 86
UVM_INFO @ 128009694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 79739380060524071802394766847581417151861878561667845061376536280406497442827 86
UVM_INFO @ 227344213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 107636980127209570215480285580477263759069106310714486235240865999120548793635 86
UVM_INFO @ 28974937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 18718362246778574662287359525986030927951572291245513749105421929771032703135 86
UVM_INFO @ 128507366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 109361164547909283257337299515530387915004983320373643413067170199483839988733 86
UVM_INFO @ 275575979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 103853933307735840666724207842956432701461309305951223595654025384588818817842 86
UVM_INFO @ 119744296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 25586243668540079788456415369002233485579250332749458256183754645972759288182 86
UVM_INFO @ 116315567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 103244319885341804152814619222295682917147611000919926094555074404255983537357 86
UVM_INFO @ 29812773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 97909580169469836123348742048444534886652132018737725851377842918274406843777 86
UVM_INFO @ 46131122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 54846647848191771390139552817694507343568693722034668011442713119761292183577 86
UVM_INFO @ 160089885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 25988100209590988873309353890156496854096631963735012712297798585306569311297 86
UVM_INFO @ 69464078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 95958216426751583284441513404377460482956891033459988322012811346031449074800 85
UVM_INFO @ 10004245136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1200) [sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
sram_ctrl_stress_all_with_rand_reset 84989574463489418454850401580407155716805683763542411062893753449516705280319 97
UVM_INFO @ 326882927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---