Simulation Results: sysrst_ctrl

 
20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.11 %
  • code
  • 98.05 %
  • assert
  • 98.85 %
  • func
  • 91.43 %
  • line
  • 98.92 %
  • branch
  • 99.04 %
  • cond
  • 98.04 %
  • toggle
  • 100.00 %
  • FSM
  • 94.23 %
Validation stages
V1
100.00%
V2
97.31%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
sysrst_ctrl_smoke 6.940s 2112.495us 10 10 100.00
input_output_inverted 10 10 100.00
sysrst_ctrl_in_out_inverted 7.240s 2474.037us 10 10 100.00
combo_detect_ec_rst 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst 5.470s 2396.074us 5 5 100.00
combo_detect_ec_rst_with_pre_cond 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 7.270s 2334.965us 5 5 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 7.440s 4040.978us 1 1 100.00
csr_rw 5 5 100.00
sysrst_ctrl_csr_rw 5.310s 2039.538us 5 5 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 28.060s 11321.283us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 5.600s 2502.567us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 7.620s 2069.055us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sysrst_ctrl_csr_rw 5.310s 2039.538us 5 5 100.00
sysrst_ctrl_csr_aliasing 5.600s 2502.567us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 25 25 100.00
sysrst_ctrl_combo_detect 353.980s 177320.250us 25 25 100.00
combo_detect_with_pre_cond 93 100 93.00
sysrst_ctrl_combo_detect_with_pre_cond 381.520s 197002.249us 93 100 93.00
auto_block_key_outputs 25 25 100.00
sysrst_ctrl_auto_blk_key_output 270.800s 488441.371us 25 25 100.00
keyboard_input_triggered_interrupt 50 50 100.00
sysrst_ctrl_edge_detect 620.230s 431398.593us 50 50 100.00
pin_output_keyboard_inversion_control 10 10 100.00
sysrst_ctrl_pin_override_test 8.580s 2511.052us 10 10 100.00
pin_input_value_accessibility 10 10 100.00
sysrst_ctrl_pin_access_test 4.440s 2189.711us 10 10 100.00
ec_power_on_reset 10 10 100.00
sysrst_ctrl_ec_pwr_on_rst 13.470s 5097.073us 10 10 100.00
flash_write_protect_output 10 10 100.00
sysrst_ctrl_flash_wr_prot_out 8.280s 2610.275us 10 10 100.00
ultra_low_power_test 23 25 92.00
sysrst_ctrl_ultra_low_pwr 103.030s 2770139.367us 23 25 92.00
sysrst_ctrl_feature_disable 2 2 100.00
sysrst_ctrl_feature_disable 87.290s 37833.660us 2 2 100.00
stress_all 10 10 100.00
sysrst_ctrl_stress_all 538.150s 1036498.589us 10 10 100.00
alert_test 10 10 100.00
sysrst_ctrl_alert_test 7.210s 2016.124us 10 10 100.00
intr_test 10 10 100.00
sysrst_ctrl_intr_test 6.850s 2017.041us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sysrst_ctrl_tl_errors 9.110s 2047.504us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sysrst_ctrl_tl_errors 9.110s 2047.504us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sysrst_ctrl_csr_hw_reset 7.440s 4040.978us 1 1 100.00
sysrst_ctrl_csr_rw 5.310s 2039.538us 5 5 100.00
sysrst_ctrl_csr_aliasing 5.600s 2502.567us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 24.540s 7924.874us 5 5 100.00
tl_d_partial_access 12 12 100.00
sysrst_ctrl_csr_hw_reset 7.440s 4040.978us 1 1 100.00
sysrst_ctrl_csr_rw 5.310s 2039.538us 5 5 100.00
sysrst_ctrl_csr_aliasing 5.600s 2502.567us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 24.540s 7924.874us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
sysrst_ctrl_sec_cm 95.540s 42012.012us 5 5 100.00
sysrst_ctrl_tl_intg_err 98.840s 42406.960us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
sysrst_ctrl_tl_intg_err 98.840s 42406.960us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
sysrst_ctrl_stress_all_with_rand_reset 21.950s 13646.346us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) 3 test runs
sysrst_ctrl_combo_detect_with_pre_cond 95564756430346039453569583050777242838854806464379606216236823100029340936804 680
UVM_ERROR @ 30015695228 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 30015695228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_combo_detect_with_pre_cond 3457945720647922098860673946088219277860591654399378925229476061035414492637 694
UVM_ERROR @ 39637464256 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 39637464256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_combo_detect_with_pre_cond 62402240918428167906734386050574490316105349210531842922237036161921581164460 677
UVM_ERROR @ 25428464566 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 25428464566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)  2 test runs
sysrst_ctrl_ultra_low_pwr 72302940918514127684005472328776565781668724673524303773741336871015127999452 655
UVM_INFO @ 2357979719 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
UVM_INFO @ 4453197294 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 4469617294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_ultra_low_pwr 41437720479450847415448446823484279139941234153313945965095531224793872216089 655
UVM_ERROR @ 5077047417 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 5077047417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-* 2 test runs
sysrst_ctrl_combo_detect_with_pre_cond 47942633839855338677659050284306035844081495924389014290835969847517973157179 699
UVM_INFO @ 54400797329 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x32
UVM_INFO @ 54400917329 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x30
UVM_INFO @ 56189087329 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2
UVM_INFO @ 56189087329 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3
sysrst_ctrl_combo_detect_with_pre_cond 10835815438251473111080672677656809481287940810703898045301363521078739087585 666
UVM_ERROR @ 24061865666 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-4
UVM_INFO @ 24061865666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*]) 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 59023265327682026480829866063027888595528076012382992506199894511616982741046 670
UVM_ERROR @ 27974501045 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 2 [0x2])
UVM_INFO @ 27974501045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(8) vs exp(3) +/-* 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 93277516646052713298220879207141243697225577882249258517103575175588414710844 665
UVM_ERROR @ 12856863578 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-4
UVM_INFO @ 12856863578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---