Simulation Results

Simulation Results: uart

20/06/2026 02:47:04 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.96 %

code
92.64 %

assert
98.85 %

func
99.39 %

line
99.48 %

branch
98.14 %

cond
98.25 %

toggle
74.67 %

Validation stages

V1		100.00%
V2		96.47%
V2S		100.00%
V3		95.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	uart_smoke	25.230s	6015.365us	10	10	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	0.930s	45.241us	1	1	100.00
csr_rw				5	5	100.00
	uart_csr_rw	0.960s	23.415us	5	5	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	1.690s	127.134us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	1.050s	171.510us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	uart_csr_mem_rw_with_rand_reset	1.230s	59.678us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	uart_csr_rw	0.960s	23.415us	5	5	100.00
	uart_csr_aliasing	1.050s	171.510us	1	1	100.00

383/397 passed

96.47 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				10	10	100.00
	uart_tx_rx	92.620s	153470.765us	10	10	100.00
parity				20	20	100.00
	uart_smoke	25.230s	6015.365us	10	10	100.00
	uart_tx_rx	92.620s	153470.765us	10	10	100.00
parity_error				20	20	100.00
	uart_intr	274.110s	493640.748us	10	10	100.00
	uart_rx_parity_err	181.480s	355479.505us	10	10	100.00
watermark				20	20	100.00
	uart_tx_rx	92.620s	153470.765us	10	10	100.00
	uart_intr	274.110s	493640.748us	10	10	100.00
fifo_full				10	10	100.00
	uart_fifo_full	151.430s	141166.578us	10	10	100.00
fifo_overflow				9	10	90.00
	uart_fifo_overflow	125.490s	156268.026us	9	10	90.00
fifo_reset				199	200	99.50
	uart_fifo_reset	346.200s	231314.351us	199	200	99.50
rx_frame_err				10	10	100.00
	uart_intr	274.110s	493640.748us	10	10	100.00
rx_break_err				10	10	100.00
	uart_intr	274.110s	493640.748us	10	10	100.00
rx_timeout				10	10	100.00
	uart_intr	274.110s	493640.748us	10	10	100.00
perf				9	10	90.00
	uart_perf	769.190s	25008.416us	9	10	90.00
sys_loopback				10	10	100.00
	uart_loopback	14.550s	10143.003us	10	10	100.00
line_loopback				10	10	100.00
	uart_loopback	14.550s	10143.003us	10	10	100.00
rx_noise_filter				0	10	0.00
	uart_noise_filter	26.970s	57659.324us	0	10	0.00
rx_start_bit_filter				10	10	100.00
	uart_rx_start_bit_filter	60.770s	48139.892us	10	10	100.00
tx_overide				10	10	100.00
	uart_tx_ovrd	7.670s	8035.097us	10	10	100.00
rx_oversample				10	10	100.00
	uart_rx_oversample	30.540s	5887.600us	10	10	100.00
long_b2b_transfer				10	10	100.00
	uart_long_xfer_wo_dly	786.790s	122287.637us	10	10	100.00
stress_all				9	10	90.00
	uart_stress_all	574.980s	252502.317us	9	10	90.00
alert_test				10	10	100.00
	uart_alert_test	0.920s	14.226us	10	10	100.00
intr_test				10	10	100.00
	uart_intr_test	0.950s	57.914us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	uart_tl_errors	2.730s	520.763us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	uart_tl_errors	2.730s	520.763us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	uart_csr_hw_reset	0.930s	45.241us	1	1	100.00
	uart_csr_rw	0.960s	23.415us	5	5	100.00
	uart_csr_aliasing	1.050s	171.510us	1	1	100.00
	uart_same_csr_outstanding	1.090s	29.293us	5	5	100.00
tl_d_partial_access				12	12	100.00
	uart_csr_hw_reset	0.930s	45.241us	1	1	100.00
	uart_csr_rw	0.960s	23.415us	5	5	100.00
	uart_csr_aliasing	1.050s	171.510us	1	1	100.00
	uart_same_csr_outstanding	1.090s	29.293us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	uart_sec_cm	1.260s	81.586us	5	5	100.00
	uart_tl_intg_err	1.730s	89.985us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	uart_tl_intg_err	1.730s	89.985us	25	25	100.00

19/20 passed

95.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				19	20	95.00
	uart_stress_all_with_rand_reset	62.770s	3259.060us	19	20	95.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *				6 test runs
	uart_noise_filter	31025306349825964129590696634466599264263268628241182590744636654404399628785	74	UVM_ERROR @ 26971288 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 104958873 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr UVM_ERROR @ 104958873 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr UVM_ERROR @ 116638970 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
	uart_noise_filter	47512440884871040510823161832138149075633221874043300954441481496491374283058	74	UVM_ERROR @ 61599677 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_INFO @ 122195979 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 1/3 UVM_ERROR @ 1893849174 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr UVM_INFO @ 3056250778 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 2/3
	uart_stress_all	48145302188293059712853105376835463842138474819327904537817147816092113834617	88	UVM_ERROR @ 129854806231 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 130195425703 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 130195425703 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 130380504847 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 2 (+/-1), act: 4, clk_pulses: 0
	uart_noise_filter	66591367393480246845167595808823502268825633045232348060399076889846895692910	77	UVM_ERROR @ 9562229253 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 9610869253 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1 UVM_ERROR @ 9610869253 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 9611869253 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
	uart_noise_filter	4988626807239701717824284977302537104242852882677601434511973712058454356456	76	UVM_ERROR @ 4757430695 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 5908634199 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1 UVM_ERROR @ 5997168282 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0 UVM_ERROR @ 6027658841 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
	uart_noise_filter	25900197447960572071202465820975586954650759717224168303196231504392044675551	74	UVM_ERROR @ 33648747 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 39187203 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 39187203 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 378879171 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: , clk_pulses:				5 test runs
	uart_noise_filter	78052655674359694734899626222782616408046619232728300548511172318685798418676	75	UVM_ERROR @ 227834902 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 227900122 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (107 [0x6b] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 380319262 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0 UVM_ERROR @ 380341002 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
	uart_noise_filter	93191916539724935678687136010809785856106213449171570594165992429735573004230	76	UVM_ERROR @ 5577052136 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 5577909284 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (111 [0x6f] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 5578052142 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 5578480716 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (111 [0x6f] vs 127 [0x7f]) reg name: uart_reg_block.rdata
	uart_noise_filter	41892902741185197337440312646533674024840018671346479655254585923718120167416	74	UVM_ERROR @ 1430118373 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 1431451705 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 95 [0x5f]) reg name: uart_reg_block.rdata UVM_ERROR @ 2219895361 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 2219895361 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_noise_filter	7235890428805823694499396887389371577086502941087543777988096523575380880529	74	UVM_ERROR @ 355755373 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 355875373 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 231 [0xe7]) reg name: uart_reg_block.rdata UVM_ERROR @ 1104755373 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0 UVM_ERROR @ 1104835373 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
	uart_noise_filter	72286402602671023884822681911807211413914035812652050026382075544391706605008	78	UVM_ERROR @ 16145603830 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 16145803830 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (196 [0xc4] vs 190 [0xbe]) reg name: uart_reg_block.rdata UVM_ERROR @ 17296563830 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 17296563830 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [] vs [*]) Interrupt_pin: TxEmpty				4 test runs
	uart_stress_all_with_rand_reset	103402244061011593469969317410845539174650169928683366615076766642402543154834	103	UVM_INFO @ 2167354837 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/407 UVM_INFO @ 2246780231 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Issuing reset for run 3/10 UVM_INFO @ 2246873255 ps: (cip_base_vseq.sv:1223) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
	uart_fifo_overflow	77469585220681633334526208388829174593618748090425192711777008008195604823353	74	UVM_INFO @ 5599395672 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 1/7 UVM_INFO @ 5688235672 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 2/7 UVM_INFO @ 7416915672 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 3/7 UVM_INFO @ 11358465672 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 4/7
	uart_perf	71543131779862541950505972015541171671818615330035099199855356010459593206883	77	UVM_INFO @ 8199601260 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/6 UVM_INFO @ 11691323638 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 5/6 UVM_INFO @ 12382329089 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 6/6 UVM_INFO @ 12429051722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
	uart_fifo_reset	38203203500986499489125042027682704519444692199450693856189586365241361288327	74	UVM_INFO @ 1991990916 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/8 UVM_INFO @ 7399840916 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/8 UVM_INFO @ 11630960916 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/8 UVM_INFO @ 100436062598 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/8