Simulation Results

Simulation Results: adc_ctrl

27/06/2026 02:42:03 DVSim: v1.49.0 sha: 1134d70 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
67.54 %

code
96.14 %

assert
92.71 %

func
13.76 %

line
98.86 %

branch
97.40 %

cond
87.39 %

toggle
99.76 %

FSM
97.30 %

Validation stages

V1		100.00%
V2		50.28%
V2S		100.00%
V3		0.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	adc_ctrl_smoke	15.990s	5970.358us	10	10	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	1.170s	1319.930us	1	1	100.00
csr_rw				5	5	100.00
	adc_ctrl_csr_rw	1.990s	412.336us	5	5	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	5.530s	964.940us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	2.320s	850.034us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	1.870s	421.172us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	adc_ctrl_csr_rw	1.990s	412.336us	5	5	100.00
	adc_ctrl_csr_aliasing	2.320s	850.034us	1	1	100.00

89/177 passed

50.28 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	10	0.00
	adc_ctrl_filters_polled	1.780s	386.520us	0	10	0.00
filters_polled_fixed				0	10	0.00
	adc_ctrl_filters_polled_fixed	1.980s	396.539us	0	10	0.00
filters_interrupt				0	10	0.00
	adc_ctrl_filters_interrupt	2.060s	421.881us	0	10	0.00
filters_interrupt_fixed				0	10	0.00
	adc_ctrl_filters_interrupt_fixed	2.240s	525.050us	0	10	0.00
filters_wakeup				0	10	0.00
	adc_ctrl_filters_wakeup	2.100s	446.509us	0	10	0.00
filters_wakeup_fixed				0	10	0.00
	adc_ctrl_filters_wakeup_fixed	2.070s	494.629us	0	10	0.00
filters_both				0	10	0.00
	adc_ctrl_filters_both	2.220s	515.220us	0	10	0.00
clock_gating				0	10	0.00
	adc_ctrl_clock_gating	2.030s	511.836us	0	10	0.00
poweron_counter				10	10	100.00
	adc_ctrl_poweron_counter	12.990s	5229.844us	10	10	100.00
lowpower_counter				10	10	100.00
	adc_ctrl_lowpower_counter	83.750s	32168.942us	10	10	100.00
fsm_reset				10	10	100.00
	adc_ctrl_fsm_reset	235.980s	131778.818us	10	10	100.00
stress_all				2	10	20.00
	adc_ctrl_stress_all	164.780s	102850.531us	2	10	20.00
alert_test				10	10	100.00
	adc_ctrl_alert_test	2.290s	507.458us	10	10	100.00
intr_test				10	10	100.00
	adc_ctrl_intr_test	1.890s	397.878us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	adc_ctrl_tl_errors	3.620s	595.767us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	adc_ctrl_tl_errors	3.620s	595.767us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	adc_ctrl_csr_hw_reset	1.170s	1319.930us	1	1	100.00
	adc_ctrl_csr_rw	1.990s	412.336us	5	5	100.00
	adc_ctrl_csr_aliasing	2.320s	850.034us	1	1	100.00
	adc_ctrl_same_csr_outstanding	10.990s	2663.480us	5	5	100.00
tl_d_partial_access				12	12	100.00
	adc_ctrl_csr_hw_reset	1.170s	1319.930us	1	1	100.00
	adc_ctrl_csr_rw	1.990s	412.336us	5	5	100.00
	adc_ctrl_csr_aliasing	2.320s	850.034us	1	1	100.00
	adc_ctrl_same_csr_outstanding	10.990s	2663.480us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	adc_ctrl_sec_cm	19.650s	7815.509us	5	5	100.00
	adc_ctrl_tl_intg_err	23.520s	8392.154us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	adc_ctrl_tl_intg_err	23.520s	8392.154us	25	25	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	adc_ctrl_stress_all_with_rand_reset	9.060s	3002.119us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				98 test runs
	adc_ctrl_filters_polled	78229366211430574184926298065510580369068846531826803143938109592039385320087	386	UVM_INFO @ 454729554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	91738154893625969608580844784577057877261985730276503140326869308832296313852	386	UVM_INFO @ 380107835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	111707781869378635382727475236682446981668450972206860519151287783612533301486	386	UVM_INFO @ 451732096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	114064809190382179783318548293710159257069236741118935756350052688812641171702	386	UVM_INFO @ 525050069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	41800438464524280343471251346940589741831892968920105635355770927335865520911	386	UVM_INFO @ 364261395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	95404436690374610575296839367142488322977596287632399283348369310448326329287	386	UVM_INFO @ 286380097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	33364195602867917788243258927074742403290773902645035506582962099162296000359	386	UVM_INFO @ 511835597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	23873713720757788860005519940327223215862234328240872630270767359677137549021	386	UVM_INFO @ 320107576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	113198907159525134669555155596939939740470957816506526251630311209297447512338	392	UVM_INFO @ 771606348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	78627607866957420537205782043611402663806946648970748817622984999092225915462	414	UVM_INFO @ 102850530847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	47225870888517760663205985670792473825538203645722666203846430401670686498050	386	UVM_INFO @ 303627825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	16022806210227232637333044460114119230145372005701164533519757695054323572999	386	UVM_INFO @ 396539352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	21739554234540263258179838655095047077330551600571236349062238086722319076749	386	UVM_INFO @ 319574359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	22468783262342493050319184233393795048519738004852565411284222364069989198716	386	UVM_INFO @ 412632539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	18273523515347070485834716206381967345914536066811575804904015056654515718168	386	UVM_INFO @ 423636833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	3530237969741987690359536698605712515002930162466013214053442916610729475197	386	UVM_INFO @ 494628504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	100345301295613701737839578187675336924516267651598737289600129266850929056532	386	UVM_INFO @ 383092449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	111132435241326148229994310744232963968570315768255341415343337171178308158756	386	UVM_INFO @ 500279575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	88879495135722020894340559456423803236448954629473033088313947824068730692985	399	UVM_INFO @ 1032810204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	32213384422436437723000732423780075145799793045096693339770722560857727397684	476	UVM_INFO @ 34450880836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	104793093374924761439246668477803055124509284433253599022483425382945267858942	386	UVM_INFO @ 343663581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	109699493371303983188197900333841214294634600745727270646187224936836870301526	386	UVM_INFO @ 412613949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	81206964208332764855212645654221907728147564885501634725946911239488330071872	386	UVM_INFO @ 510871139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	35765320972346811706114372967187388106932893592311271825609088614197087230377	386	UVM_INFO @ 328719686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	5743207314132371372839057371463519771285863617342522762312925808546869772583	386	UVM_INFO @ 503686962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	18460396601572317193954037460380206639200225477188703661877454558340162980369	386	UVM_INFO @ 347849963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	61571054519606753600178971294780243650346691490257866110126175490915078957947	386	UVM_INFO @ 459410344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	71360349294113751950722685550678182137372957506246469354681557492673359874189	386	UVM_INFO @ 455859875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	38828586968395897478181712603013061752475817058484988092061494413265924046879	415	UVM_INFO @ 4522767289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	55357239356221161725743025988691010499584448960580947892376970557558368523096	386	UVM_INFO @ 317808425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	82444095704632941220867901383750604386440913272846232549253728353436971166262	386	UVM_INFO @ 434875819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	41075204056529950612839899948178432667861215310486574874721745164503024202545	386	UVM_INFO @ 388485723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	16706255784960498484722188133774648849310607326912593304716105276668538118296	386	UVM_INFO @ 417326004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	16317814536067875016618366035738854632645477664583157267000218661616775612123	386	UVM_INFO @ 299562123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	81636292360212466868909898806767786666457309267304174635401843774386674559417	386	UVM_INFO @ 357792182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	54014263727892507627722728894822492942445866141737992038092232941220107830834	386	UVM_INFO @ 514410106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	99391510436652876128601559600274958322175831153225163796994542362625106572177	386	UVM_INFO @ 467692785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	110321753118268336341453738829047036258945016805001531819725417402852917467469	399	UVM_INFO @ 807859740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	85235753455540758444216985766982723266200262942794877409631374204192398410500	387	UVM_INFO @ 828480457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	4671540512684166758531488228985837019079956607369455238643936338138616573628	386	UVM_INFO @ 288077138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	44909508311696368152479954782617392198502765417985485889777623711318307088507	386	UVM_INFO @ 285839454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	5275418171806208165023052257960318520192385840987155198521039591810744465641	386	UVM_INFO @ 267590738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	90249200115994671883931044626158040451444164993848360476119299040203599936181	386	UVM_INFO @ 309295806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	37514421374187392723588006107824778488585000618719375321336598223321709090072	386	UVM_INFO @ 446509463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	105438322388710188440555372881122924526114142534678631737705825500659307808822	386	UVM_INFO @ 387147421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	35381735652335620155486617225542261910076560257990707134196285718221305556458	386	UVM_INFO @ 300319297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	8350503603571905421936694977161477700004131726806176355132370297197474885767	386	UVM_INFO @ 495434805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	41737201027858076657899981064908982116544512392723752939159912417982649084701	409	UVM_INFO @ 1147463995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	35834330455502212210717125855134959210117972885744861213781514597049778413549	387	UVM_INFO @ 644365256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	19545378973072026425654893030250516659203586613857681047793161322969418925146	386	UVM_INFO @ 454395562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	42002279714526213050395319596386049233295671176773013788928893615294127609422	386	UVM_INFO @ 487257202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	105882635588035697098343811006131285103073286384928343882507822192729885915524	386	UVM_INFO @ 387673669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	6645349820061072990285776555550087543256663832304753742767607956409211309524	386	UVM_INFO @ 450902286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	53599272970316536203983958015194793263816059179256227536390076960066631650137	386	UVM_INFO @ 516262724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	16382494424767196774135395400572480606481953894657389050598576728550396976522	386	UVM_INFO @ 383015256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	106496065615234274515745092318583706286054197908337264687334422038813487404309	386	UVM_INFO @ 461631659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	58747935627059630857248690524803950305302403679293780635692694377411627129058	386	UVM_INFO @ 335835950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	102316945246265002024628948719693548290288137927325193404920792505673564640189	414	UVM_INFO @ 3002119203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	2334269699775214252202450640269698098143074062305533835901842254474687181401	414	UVM_INFO @ 144566445892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	71090048239848307864691054778764959075261909043331520046285668638354590165248	386	UVM_INFO @ 316191261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	102724164954392220657597229925888077627001155595658855365696369078557486953873	386	UVM_INFO @ 316226039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	14258535032034683403587065225864252265560653290778635407871053051176342368095	386	UVM_INFO @ 340419130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	21483329252668318855945200297302983526279779093074850461519349189694245317306	386	UVM_INFO @ 416962020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	79903190559896875197579590212661699223316310408379547406098492022533002373215	386	UVM_INFO @ 300937895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	92996354313652015712855023410896889338185024395343462609334556875338034291134	386	UVM_INFO @ 410932828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	109136598172101948546809864912486159179758438061682131594411734087409729593000	386	UVM_INFO @ 325620982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	10730533699888822427055875960587010965896481327682126747344351424194921438159	386	UVM_INFO @ 431837890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	104039790677083607687293196630513956608473873267930465359510390309455854704495	457	UVM_INFO @ 7612767023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	22678583781702929726031897790882891600296641470643657702531010066949077415951	386	UVM_INFO @ 316248332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	56293918661802299621327098980837840759679539365622227754015095640299634688403	386	UVM_INFO @ 283392273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	94545609050091271514289430005453717856978467056066929836348242110195999991350	386	UVM_INFO @ 408161780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	93727784406323421077747417201779556171516920224474009847246566548781798237847	386	UVM_INFO @ 431188220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	60257886528880187726010336749122703395288274727820740709500349239467184011951	386	UVM_INFO @ 424375395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	5961164276965458879547508893740953837612389902217073944061192001404099883797	386	UVM_INFO @ 338327332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	46621786327923652274543558835738769941086266197828497400176473032063671613537	386	UVM_INFO @ 358611868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	38102177037198399709196922636577067392495431071176673401764760242450946457647	386	UVM_INFO @ 515219528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	49657772292673506717777129049789851136289101310047720359459657817031590599458	399	UVM_INFO @ 879137565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	35826312628617744901582295710404987630815844420983223246972715045659876748329	387	UVM_INFO @ 788267630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	81527406766776345697568260020305493959628931073743184737990479643516861550381	386	UVM_INFO @ 386520346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	45210326280180824229306559647791251407547789302146442407515865894584539214905	386	UVM_INFO @ 421420856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	51412857805055605047847943143973571448408157950520411380461462915856302697038	386	UVM_INFO @ 421881211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	67283944582847229660718267723558039375773689677368227196505699987424430560076	386	UVM_INFO @ 487867303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	91297692987989522038051556742502228240031445670145474295373553794314586654502	386	UVM_INFO @ 292900277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	101828867058757944748843388798194726810405434798157601404558245299957337330367	386	UVM_INFO @ 302950206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	98260018869637108523755662941070921593882339553379142399053497822157072999545	386	UVM_INFO @ 283923323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	51906931340159605065974911868028385034688371929037193420107309992143076165151	386	UVM_INFO @ 443420320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	55793859819305905701188163307048417573234792190306676090330985749099698026607	399	UVM_INFO @ 799929552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	85361014795552617278343189464261301366254607493476664324942294289492474362752	387	UVM_INFO @ 714443816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	26123599067281255077364511847965783219426910531867436211173386198904232943165	386	UVM_INFO @ 345759864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	85122987236333426607601614051833710566684005329097700268050906190914468766282	386	UVM_INFO @ 307731153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	82453603737680109055038673330075907093469731319288053492096179751654897252652	386	UVM_INFO @ 407419257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	61149508937641842794550958507347767568719331793116758995409017157533340602214	386	UVM_INFO @ 371107607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	68780204543468376272101028380338875815948811980637506526862585809011320099206	386	UVM_INFO @ 337501385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	98701192089146252269248001693774890156638366078874987797678782658695811982202	386	UVM_INFO @ 398890603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	14086376690876143990124914821194079205259713401426069437316091229532328573619	386	UVM_INFO @ 304912273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	80350292408036627692383742756955086248082873195031350128845115525477663333920	386	UVM_INFO @ 304426689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	109308177688283707157022680639803653368080835113897790756395728593399004225898	406	UVM_INFO @ 1114721064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	40767001556328158380871341659629476196293933721693483446890847950595720046334	387	UVM_INFO @ 908623030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---