| V1 |
|
100.00% |
| V2 |
|
89.15% |
| V2S |
|
99.02% |
| V3 |
|
60.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 55.290s | 984.605us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 5.910s | 239.007us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| alert_handler_csr_rw | 10.570s | 118.783us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 126.810s | 4599.677us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 39.180s | 548.569us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 10.840s | 134.788us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| alert_handler_csr_rw | 10.570s | 118.783us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 39.180s | 548.569us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 25 | 25 | 100.00 | |||
| alert_handler_esc_alert_accum | 316.490s | 27155.479us | 25 | 25 | 100.00 | |
| esc_timeout | 50 | 50 | 100.00 | |||
| alert_handler_esc_intr_timeout | 77.370s | 1370.308us | 50 | 50 | 100.00 | |
| entropy | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 2716.690s | 128267.992us | 25 | 25 | 100.00 | |
| sig_int_fail | 49 | 50 | 98.00 | |||
| alert_handler_sig_int_fail | 59.870s | 4942.190us | 49 | 50 | 98.00 | |
| clk_skew | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 55.290s | 984.605us | 10 | 10 | 100.00 | |
| random_alerts | 10 | 10 | 100.00 | |||
| alert_handler_random_alerts | 70.430s | 1392.352us | 10 | 10 | 100.00 | |
| random_classes | 50 | 50 | 100.00 | |||
| alert_handler_random_classes | 80.330s | 5219.939us | 50 | 50 | 100.00 | |
| ping_timeout | 19 | 50 | 38.00 | |||
| alert_handler_ping_timeout | 352.680s | 21249.159us | 19 | 50 | 38.00 | |
| lpg | 97 | 100 | 97.00 | |||
| alert_handler_lpg | 2696.370s | 132941.247us | 49 | 50 | 98.00 | |
| alert_handler_lpg_stub_clk | 3162.700s | 266918.591us | 48 | 50 | 96.00 | |
| stress_all | 50 | 50 | 100.00 | |||
| alert_handler_stress_all | 3713.600s | 105507.169us | 50 | 50 | 100.00 | |
| alert_handler_entropy_stress_test | 0 | 20 | 0.00 | |||
| alert_handler_entropy_stress | 19.460s | 1614.041us | 0 | 20 | 0.00 | |
| alert_handler_alert_accum_saturation | 20 | 20 | 100.00 | |||
| alert_handler_alert_accum_saturation | 5.650s | 68.520us | 20 | 20 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| alert_handler_intr_test | 2.260s | 13.379us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 27.600s | 376.236us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 27.600s | 376.236us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 5.910s | 239.007us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 10.570s | 118.783us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 39.180s | 548.569us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 39.120s | 2640.892us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 5.910s | 239.007us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 10.570s | 118.783us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 39.180s | 548.569us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 39.120s | 2640.892us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 328.310s | 10788.723us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 328.310s | 10788.723us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 328.310s | 10788.723us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 328.310s | 10788.723us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 1007.750s | 15942.016us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| alert_handler_sec_cm | 61.340s | 1503.718us | 5 | 5 | 100.00 | |
| alert_handler_tl_intg_err | 74.600s | 4401.529us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| alert_handler_tl_intg_err | 74.600s | 4401.529us | 25 | 25 | 100.00 | |
| sec_cm_config_shadow | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 328.310s | 10788.723us | 20 | 20 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 55.290s | 984.605us | 10 | 10 | 100.00 | |
| sec_cm_alert_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 55.290s | 984.605us | 10 | 10 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 55.290s | 984.605us | 10 | 10 | 100.00 | |
| sec_cm_class_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 55.290s | 984.605us | 10 | 10 | 100.00 | |
| sec_cm_alert_intersig_diff | 49 | 50 | 98.00 | |||
| alert_handler_sig_int_fail | 59.870s | 4942.190us | 49 | 50 | 98.00 | |
| sec_cm_lpg_intersig_mubi | 49 | 50 | 98.00 | |||
| alert_handler_lpg | 2696.370s | 132941.247us | 49 | 50 | 98.00 | |
| sec_cm_esc_intersig_diff | 49 | 50 | 98.00 | |||
| alert_handler_sig_int_fail | 59.870s | 4942.190us | 49 | 50 | 98.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 2716.690s | 128267.992us | 25 | 25 | 100.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 2716.690s | 128267.992us | 25 | 25 | 100.00 | |
| sec_cm_esc_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 61.340s | 1503.718us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 61.340s | 1503.718us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 61.340s | 1503.718us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 61.340s | 1503.718us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 61.340s | 1503.718us | 5 | 5 | 100.00 | |
| sec_cm_accu_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 61.340s | 1503.718us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 61.340s | 1503.718us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 61.340s | 1503.718us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 61.340s | 1503.718us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 6 | 10 | 60.00 | |||
| alert_handler_stress_all_with_rand_reset | 359.000s | 8726.213us | 6 | 10 | 60.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | 25 test runs | |||
| alert_handler_ping_timeout | 17840464238981331426889668924014428645154848318721766276182458403327918120135 | 108 |
UVM_INFO @ 10201380108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 80441374850593084237692434580532581606691783477871206316105532468018554918479 | 102 |
UVM_INFO @ 13427914335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 7891755011474062781961183272108616069844502446278909275179837116849177379452 | 108 |
UVM_INFO @ 36460350201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 11722566280877739600058410316300025276088488981457149437887084680388115294129 | 87 |
UVM_INFO @ 5417358019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 5943494415737942547263862968680197003630665669857381738987057555365814684211 | 87 |
UVM_INFO @ 5332133553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 40685324391855605922099437903578361616046104942872757556405072214869541457775 | 121 |
UVM_INFO @ 3779041234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 8691413906745980121079293677307124218556007246049083124091685928832368402655 | 87 |
UVM_INFO @ 7230870730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 110696179631748450013423835240292998188602306499172882568759777713810224572610 | 117 |
UVM_INFO @ 6232939143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_lpg | 26818537802140228706642724949315246550481785144871522940563650835691259912242 | 83 |
UVM_INFO @ 15738527251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 33982533137618802087217375145897604354004229313021656066028318925504095685338 | 84 |
UVM_INFO @ 3853514010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 90703732302603366036423410835922245011047561860936859776261181753171035375519 | 90 |
UVM_INFO @ 2190796175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 30842316689896392013903265660491588692457391110568152261156454810898215091467 | 102 |
UVM_INFO @ 11041224678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 53129312254672956561463302261404155633755895904027889110404826874790241955618 | 114 |
UVM_INFO @ 26952897205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 99078706148222948074578155950017791473876098738780375479753120482639976784117 | 108 |
UVM_INFO @ 7297120901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 64991854060194203157892416043607065425215969753070327171709684189020658039512 | 99 |
UVM_INFO @ 2120660835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 77496178490771022539842218640861394174499383842094861528319572076849908962295 | 95 |
UVM_INFO @ 40782488845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 89764011656466908022718833112819526418193444951807707520852712071673899726567 | 102 |
UVM_INFO @ 26138061164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 24109573365965816972041497536007674277289383720075819008361914218135257034925 | 88 |
UVM_INFO @ 1169568674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 76587613316565900153306381066103557589944564334359257822491919192511933380250 | 87 |
UVM_INFO @ 980339973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 46472359355322789496971928263746202217339414821660532992977576480827433198920 | 105 |
UVM_INFO @ 4383264996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 70136131805361072654181520210955455003118337571904212161767994170798119521817 | 90 |
UVM_INFO @ 3300529670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 21721935268621028540179253012435804924475461489983680594542003578911420142979 | 138 |
UVM_INFO @ 8879326329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 36434143679944739669531046176886208724300150773923672295012792399223766794489 | 117 |
UVM_INFO @ 6460598123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 14904207972354819951048839299942934149416488270314741381911977070151989631043 | 111 |
UVM_INFO @ 4430278178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 53610724609358116940075814737784008301864003770479893781335844289009309048583 | 129 |
UVM_INFO @ 21249158925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 20 test runs | |||
| alert_handler_entropy_stress | 28804795116215712899894285358797180362146978260621330355417106943219773155918 | 180 |
UVM_INFO @ 1287078425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 46834477083352978333340703703785306886093088731759592063020886732621525763912 | 94 |
UVM_INFO @ 594053249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 11559233293593014681035295241449499862915484966141486897713252176763028728613 | 192 |
UVM_INFO @ 81765760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 89007966360393753396049951363337961558726747746930206443718122627995193780653 | 196 |
UVM_INFO @ 664268237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 101218605031545361777444736520557544447363645890824481878244248311351377876174 | 172 |
UVM_INFO @ 514862669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 105690627400852769070447848632704417758346290227902447013194858954114670858669 | 164 |
UVM_INFO @ 1614040879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 47975821385648844957204143911140111134891145757972095109085420215249725651714 | 192 |
UVM_INFO @ 170858280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 8109957938021451598646757148045361832046750952312704549012092089576230198620 | 142 |
UVM_INFO @ 598929710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 40401047196845133271369443968159864043389630624367827874624437257462048593878 | 144 |
UVM_INFO @ 308741194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 76579142739087136827527533175044938818064927980973941774110623806599343606309 | 194 |
UVM_INFO @ 223402848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 13834448620357889151517963518599589416113456788440431701155657374623406427616 | 202 |
UVM_INFO @ 205271958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 74963605446767547124967116906025733497184181118017048354068573105056473229137 | 192 |
UVM_INFO @ 1518839346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 69255020498979855314264322883270416455936779715799529864945055439172855421075 | 174 |
UVM_INFO @ 2015361631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 70795185143369166807885769535516403365494720328882897877240947416133078413746 | 186 |
UVM_INFO @ 1316976139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 81025094900557495369626097340523423157955586158150468251811892853058441069624 | 168 |
UVM_INFO @ 267044944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 75576347751966997922242664477279019187416548617293987819599662926172666428300 | 156 |
UVM_INFO @ 1116830977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 48133599967973255187138018195775502687135383122526854445823592810014054500365 | 174 |
UVM_INFO @ 785686895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 97004800126067261981816322100224100110633801076794585146826142552966423272352 | 174 |
UVM_INFO @ 2477205878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 32624438319945932814500648474593302727396432901183190056243680269100281134335 | 200 |
UVM_INFO @ 1520990599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 69084790171604370030890532233163295000813463834560375247464335478708124558238 | 166 |
UVM_INFO @ 622987038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. | 7 test runs | |||
| alert_handler_ping_timeout | 8097465654706636829927590602359673948814048004915566245286575009953518546386 | 80 |
UVM_INFO @ 1781728044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 114316790641820286062429709982859424275010413229333544534402280748331150537748 | 80 |
UVM_INFO @ 1307962635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_ping_timeout | 12639272645559914726236326258085367070373921134843743912924132695877394875172 | 80 |
UVM_INFO @ 983603951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_ping_timeout | 37533589702070686291318705308537703524198771114054593778701190824344373610424 | 80 |
UVM_INFO @ 1579590208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_ping_timeout | 4343108609387531413972064186829633674203718317390757896810618276174057731128 | 80 |
UVM_INFO @ 228082058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 56727134844654473210391952304446522393496748792622822866439630080066283116605 | 80 |
UVM_INFO @ 551640007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 32032340720946021524660725173089884312452350444436669229517481099751928662372 | 80 |
UVM_INFO @ 39053475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 3 test runs | |||
| alert_handler_stress_all_with_rand_reset | 67103302560497980516328018260666057389958394456359372079582954580576079048147 | 83 |
UVM_INFO @ 211333248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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|
| alert_handler_stress_all_with_rand_reset | 89103971470265240068636154331173072012532825636765220538969760928557298985734 | 135 |
UVM_INFO @ 1647622816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| alert_handler_stress_all_with_rand_reset | 50894241227081223985860957600942486155932621712876529216145961502813468314478 | 83 |
UVM_INFO @ 556618799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (cip_base_vseq.sv:1199) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. | 1 test run | |||
| alert_handler_stress_all_with_rand_reset | 1837460293731045240331948424151763067886904111236694101466955497882414593395 | 116 |
UVM_INFO @ 780249526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.loc_alert_cause_* | 1 test run | |||
| alert_handler_lpg_stub_clk | 36325093945690907619238260829715333582539357777888097730039999563101648256765 | 81 |
UVM_INFO @ 85251410016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalEscIntFail) | 1 test run | |||
| alert_handler_sig_int_fail | 76878949108892806038111339367621533605285698187440893358850022447546219825155 | 83 |
UVM_INFO @ 144066165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 1 test run | |||
| alert_handler_lpg_stub_clk | 100930360807950304847265064072980888860164206953909194832806026649945892835028 | 80 |
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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