Simulation Results: clkmgr

 
27/06/2026 02:42:03 DVSim: v1.49.0 sha: 1134d70 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.90 %
  • code
  • 98.64 %
  • assert
  • 95.76 %
  • func
  • 87.31 %
  • line
  • 99.12 %
  • branch
  • 98.85 %
  • cond
  • 96.06 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
77.93%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
clkmgr_smoke 1.630s 125.141us 10 10 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.000s 16.790us 1 1 100.00
csr_rw 5 5 100.00
clkmgr_csr_rw 1.180s 57.903us 5 5 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 20.980s 5117.191us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.720s 99.291us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
clkmgr_csr_mem_rw_with_rand_reset 2.540s 340.040us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
clkmgr_csr_rw 1.180s 57.903us 5 5 100.00
clkmgr_csr_aliasing 1.720s 99.291us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 10 10 100.00
clkmgr_peri 1.250s 56.072us 10 10 100.00
trans_enables 10 10 100.00
clkmgr_trans 1.770s 128.046us 10 10 100.00
extclk 10 10 100.00
clkmgr_extclk 2.470s 353.472us 10 10 100.00
clk_status 10 10 100.00
clkmgr_clk_status 1.120s 83.960us 10 10 100.00
jitter 10 10 100.00
clkmgr_smoke 1.630s 125.141us 10 10 100.00
frequency 10 10 100.00
clkmgr_frequency 13.810s 2117.564us 10 10 100.00
frequency_timeout 10 10 100.00
clkmgr_frequency_timeout 11.650s 1816.434us 10 10 100.00
frequency_overflow 10 10 100.00
clkmgr_frequency 13.810s 2117.564us 10 10 100.00
stress_all 10 10 100.00
clkmgr_stress_all 91.410s 16224.110us 10 10 100.00
alert_test 10 10 100.00
clkmgr_alert_test 1.640s 187.136us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
clkmgr_tl_errors 4.060s 278.280us 25 25 100.00
tl_d_illegal_access 25 25 100.00
clkmgr_tl_errors 4.060s 278.280us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
clkmgr_csr_hw_reset 1.000s 16.790us 1 1 100.00
clkmgr_csr_rw 1.180s 57.903us 5 5 100.00
clkmgr_csr_aliasing 1.720s 99.291us 1 1 100.00
clkmgr_same_csr_outstanding 2.890s 393.582us 5 5 100.00
tl_d_partial_access 12 12 100.00
clkmgr_csr_hw_reset 1.000s 16.790us 1 1 100.00
clkmgr_csr_rw 1.180s 57.903us 5 5 100.00
clkmgr_csr_aliasing 1.720s 99.291us 1 1 100.00
clkmgr_same_csr_outstanding 2.890s 393.582us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 14 30 46.67
clkmgr_sec_cm 51.340s 10012.578us 0 5 0.00
clkmgr_tl_intg_err 71.480s 10009.183us 14 25 56.00
shadow_reg_update_error 11 20 55.00
clkmgr_shadow_reg_errors 965.050s 200000.000us 11 20 55.00
shadow_reg_read_clear_staged_value 11 20 55.00
clkmgr_shadow_reg_errors 965.050s 200000.000us 11 20 55.00
shadow_reg_storage_error 11 20 55.00
clkmgr_shadow_reg_errors 965.050s 200000.000us 11 20 55.00
shadowed_reset_glitch 11 20 55.00
clkmgr_shadow_reg_errors 965.050s 200000.000us 11 20 55.00
shadow_reg_update_error_with_csr_rw 15 20 75.00
clkmgr_shadow_reg_errors_with_csr_rw 935.800s 200000.000us 15 20 75.00
sec_cm_bus_integrity 14 25 56.00
clkmgr_tl_intg_err 71.480s 10009.183us 14 25 56.00
sec_cm_meas_clk_bkgn_chk 10 10 100.00
clkmgr_frequency 13.810s 2117.564us 10 10 100.00
sec_cm_timeout_clk_bkgn_chk 10 10 100.00
clkmgr_frequency_timeout 11.650s 1816.434us 10 10 100.00
sec_cm_meas_config_shadow 11 20 55.00
clkmgr_shadow_reg_errors 965.050s 200000.000us 11 20 55.00
sec_cm_idle_intersig_mubi 10 10 100.00
clkmgr_idle_intersig_mubi 1.550s 187.695us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
clkmgr_lc_ctrl_intersig_mubi 1.470s 160.651us 10 10 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.430s 101.364us 10 10 100.00
sec_cm_clk_handshake_intersig_mubi 8 10 80.00
clkmgr_clk_handshake_intersig_mubi 1.390s 242.837us 8 10 80.00
sec_cm_div_intersig_mubi 10 10 100.00
clkmgr_div_intersig_mubi 1.580s 137.692us 10 10 100.00
sec_cm_jitter_config_mubi 5 5 100.00
clkmgr_csr_rw 1.180s 57.903us 5 5 100.00
sec_cm_idle_ctr_redun 0 5 0.00
clkmgr_sec_cm 51.340s 10012.578us 0 5 0.00
sec_cm_meas_config_regwen 5 5 100.00
clkmgr_csr_rw 1.180s 57.903us 5 5 100.00
sec_cm_clk_ctrl_config_regwen 5 5 100.00
clkmgr_csr_rw 1.180s 57.903us 5 5 100.00
prim_count_check 0 5 0.00
clkmgr_sec_cm 51.340s 10012.578us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 10 10 100.00
clkmgr_regwen 6.900s 1708.945us 10 10 100.00
stress_all_with_rand_reset 10 10 100.00
clkmgr_stress_all_with_rand_reset 70.870s 5182.295us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 13 test runs
clkmgr_sec_cm 91799705359762894444202110291489216325226794832489141398302624481407725987031 84
UVM_INFO @ 10012578286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 97447894765293292993642202203220021105885194053980807117650172488151374327301 81
UVM_INFO @ 10016290824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 57704266899343073173019132018011207055713775915686434721946199434550374604237 98
UVM_INFO @ 10035640839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 28142425576516394416639579212535763958836186312529797841781940993069099366792 89
UVM_INFO @ 10024936911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 35113777448163328487385818807447578188238376958346485844573125145129510610549 158
UVM_INFO @ 10178132337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 34423446644339809915492710316389263268481316033502209824624005882272061628957 128
UVM_INFO @ 10048415448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 92670363670527453544162727438149381246956253589150922657955882252644508857946 129
UVM_INFO @ 10039062228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 80173791213479477532748287177024650562387987906204302574159113022559648335804 98
UVM_INFO @ 10016148282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 75743618443501065092856484476944967694171777123195945097537790301914620883957 231
UVM_INFO @ 10204593966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 19872295306957082723426040905041959976046798273335249121820503193464867564177 100
UVM_INFO @ 10035264594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 16148608326052446540474110637198289724729176422660530143928600645823328117373 128
UVM_INFO @ 10110976942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 57247084695757234367406848629419206332027099773184090268195695690952245252676 105
UVM_INFO @ 10052339397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 11484363645317843592598748823588115835556177877388109159926019638847665227489 89
UVM_INFO @ 10009183391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 11 test runs
clkmgr_shadow_reg_errors 99579985900261265570243547401113318771136809832387783450017376655266616561925 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 47380859987896104935884078043043840511040969569887256291628471590040709178067 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 35634366717054077963606523903411885777485234805950323612803131387947915252141 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 77596263423291375280266702832135443684070157778008557041906238046167044404527 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 16300305414722470228420983746358616223210886779276713384586327209975041847621 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 110944780563647477114526022374453701982888677000138361986000113614055271054632 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 93977471417795091176120736990454903354798364471256376162054293929423568565963 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 101204516994796265236639730323097439201120192165424028893062794960026109451265 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 82477025020228000442058704596949633420940210035788530951590661947780501847361 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 99703260562300552450753125831442579611563522658264732618883480302886426944956 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 114039202430203893326582588122620549942037024334818138175449741680206978504806 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 3 test runs
clkmgr_sec_cm 112424253010996655837916231996874557853524677580875033593031073059730076570054 81
UVM_INFO @ 14444844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 18107093955788792320678560061127681813774280273391203447071231550239194321189 93
UVM_INFO @ 18295483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 39717035675040354241802017188474024151300068547335018679364819697288244675634 193
UVM_INFO @ 189463351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch 2 test runs
clkmgr_clk_handshake_intersig_mubi 40110264486589357713055585276544917785046167932616065896004573160474790584383 74
UVM_INFO @ 6157127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_clk_handshake_intersig_mubi 71386806467470720193482030668350110015784180461242066392562410987464836891661 74
UVM_INFO @ 10215618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.measure_ctrl_regwen (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 63878973886999169258994080796414533863687828158202360580892374662969188580995 76
UVM_INFO @ 2250740887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 109187273870069441642228280633110217120526101220877762172930597620548633446840 76
UVM_INFO @ 113243174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.clk_enables (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 20026406808530301191257510757791628949698325122223162470681314298110274876088 75
UVM_INFO @ 2084574229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---