Simulation Results

Simulation Results: csrng

27/06/2026 02:42:03 DVSim: v1.49.0 sha: 1134d70 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.58 %

code
96.17 %

assert
96.94 %

func
90.62 %

block
98.49 %

line
99.50 %

branch
96.30 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		98.16%
V2S		98.83%
V3		0.00%

38/38 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				25	25	100.00
	csrng_smoke	16.000s	86.359us	25	25	100.00
csr_hw_reset				1	1	100.00
	csrng_csr_hw_reset	34.000s	84.268us	1	1	100.00
csr_rw				5	5	100.00
	csrng_csr_rw	35.000s	71.559us	5	5	100.00
csr_bit_bash				1	1	100.00
	csrng_csr_bit_bash	45.000s	640.373us	1	1	100.00
csr_aliasing				1	1	100.00
	csrng_csr_aliasing	36.000s	213.072us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	csrng_csr_mem_rw_with_rand_reset	35.000s	40.580us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	csrng_csr_rw	35.000s	71.559us	5	5	100.00
	csrng_csr_aliasing	36.000s	213.072us	1	1	100.00

1283/1307 passed

98.16 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	36.000s	71.662us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	48.000s	2861.654us	500	500	100.00
err				500	500	100.00
	csrng_err	34.000s	31.290us	500	500	100.00
cmds				2	25	8.00
	csrng_cmds	67.000s	2471.932us	2	25	8.00
life cycle				2	25	8.00
	csrng_cmds	67.000s	2471.932us	2	25	8.00
stress_all				24	25	96.00
	csrng_stress_all	1484.000s	111140.232us	24	25	96.00
intr_test				10	10	100.00
	csrng_intr_test	30.000s	55.723us	10	10	100.00
alert_test				10	10	100.00
	csrng_alert_test	34.000s	16.669us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	csrng_tl_errors	13.000s	29.557us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	csrng_tl_errors	13.000s	29.557us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	csrng_csr_hw_reset	34.000s	84.268us	1	1	100.00
	csrng_csr_rw	35.000s	71.559us	5	5	100.00
	csrng_csr_aliasing	36.000s	213.072us	1	1	100.00
	csrng_same_csr_outstanding	30.000s	35.624us	5	5	100.00
tl_d_partial_access				12	12	100.00
	csrng_csr_hw_reset	34.000s	84.268us	1	1	100.00
	csrng_csr_rw	35.000s	71.559us	5	5	100.00
	csrng_csr_aliasing	36.000s	213.072us	1	1	100.00
	csrng_same_csr_outstanding	30.000s	35.624us	5	5	100.00

V2S

1270/1285 passed

98.83 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	csrng_sec_cm	18.000s	117.579us	5	5	100.00
	csrng_tl_intg_err	24.000s	1561.911us	25	25	100.00
sec_cm_config_regwen				16	30	53.33
	csrng_regwen	29.000s	2.912us	11	25	44.00
	csrng_csr_rw	35.000s	71.559us	5	5	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	48.000s	2861.654us	500	500	100.00
sec_cm_intersig_mubi				24	25	96.00
	csrng_stress_all	1484.000s	111140.232us	24	25	96.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	36.000s	71.662us	200	200	100.00
	csrng_err	34.000s	31.290us	500	500	100.00
	csrng_sec_cm	18.000s	117.579us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	36.000s	71.662us	200	200	100.00
	csrng_err	34.000s	31.290us	500	500	100.00
	csrng_sec_cm	18.000s	117.579us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	36.000s	71.662us	200	200	100.00
	csrng_err	34.000s	31.290us	500	500	100.00
	csrng_sec_cm	18.000s	117.579us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	36.000s	71.662us	200	200	100.00
	csrng_err	34.000s	31.290us	500	500	100.00
	csrng_sec_cm	18.000s	117.579us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	36.000s	71.662us	200	200	100.00
	csrng_err	34.000s	31.290us	500	500	100.00
	csrng_sec_cm	18.000s	117.579us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	48.000s	2861.654us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	36.000s	71.662us	200	200	100.00
	csrng_err	34.000s	31.290us	500	500	100.00
sec_cm_constants_lc_gated				24	25	96.00
	csrng_stress_all	1484.000s	111140.232us	24	25	96.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	48.000s	2861.654us	500	500	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	csrng_tl_intg_err	24.000s	1561.911us	25	25	100.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	36.000s	71.662us	200	200	100.00
	csrng_err	34.000s	31.290us	500	500	100.00
	csrng_sec_cm	18.000s	117.579us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	36.000s	71.662us	200	200	100.00
	csrng_err	34.000s	31.290us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	36.000s	71.662us	200	200	100.00
	csrng_err	34.000s	31.290us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	36.000s	71.662us	200	200	100.00
	csrng_err	34.000s	31.290us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	36.000s	71.662us	200	200	100.00
	csrng_err	34.000s	31.290us	500	500	100.00
	csrng_sec_cm	18.000s	117.579us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	36.000s	71.662us	200	200	100.00
	csrng_err	34.000s	31.290us	500	500	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	3600.000s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])				21 test runs
	csrng_cmds	71629970608684336921525232117613203718933058927073583617237389217049752709251	100	UVM_INFO @ 63833993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	31832839956560482888467393328265972017439836860097758546753504138922937547154	100	UVM_INFO @ 83288854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	114243812944029540702734777191550761635026891407198643573894342812213379453069	100	UVM_INFO @ 308155232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	72285705051552612329978572335260875290770556725250984325970801336049287106444	120	UVM_INFO @ 183727200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	47597439458880229860632492013166197226968764542190708659019325813220157997950	100	UVM_INFO @ 52625663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	67096377073661761679537160315569935585955187060108965223394269955963215429559	100	UVM_INFO @ 122086631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	22417849809416417579156853289599336226560438393462026350511813449894839561620	100	UVM_INFO @ 224950010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	89428950995089364830049222279447058217330911624292544528895854839361450230940	100	UVM_INFO @ 240516059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	22847512427422562091517948576005943290188996040705026829328187550201800383384	100	UVM_INFO @ 60955607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	59079439304923947596944152597817267894440406752874438313084329692797942950453	100	UVM_INFO @ 96336792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	36984000114875423702446798799152783247841222730586521948367535272751678251459	100	UVM_INFO @ 342985335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	108259971833298566878234859127958063417698955874255773299647778906824069903331	100	UVM_INFO @ 297464974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	33768672954361488240105967580644104258250173691702005139041523611230692888819	100	UVM_INFO @ 74197174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	61390369980863079273366625487407048927396593242641091449017576358420937452122	100	UVM_INFO @ 389394037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	73887840024179842395556934904179895431343173275941171386673040390722201134148	100	UVM_INFO @ 35504666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	107643693649529153831109862949358987770804114257629400369120986049569529079673	100	UVM_INFO @ 419909957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	41135873633528879456953132759545618726777732911804141963802975380300079494276	100	UVM_INFO @ 34268296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	82945391570639184179587803221192344634457008561842548524829675220977761195780	100	UVM_INFO @ 325593341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	110583913144449462671510806061313531519932789162614161612697426927534069746104	100	UVM_INFO @ 115221077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	31105095638490787511425131196400384727631710868738834358547283003750225259771	100	UVM_INFO @ 44977514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	101551413950574926646788130589918933490028777499862608053553306703208687855216	100	UVM_INFO @ 101707764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE				12 test runs
	csrng_regwen	113841451456676429505966507981238244495084947649534990820345120443065048542359	99	UVM_INFO @ 2911946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	66524569533159186802318150290971883088115335446358466775008493985788627315592	99	UVM_INFO @ 4014009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	83502880462880191187594806212400766177084971793303146097647198780299443646576	99	UVM_INFO @ 3055474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	42701757988992993507680813582849399504914562739647567006832252590666924956200	99	UVM_INFO @ 2667001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	52031820605045244527305162727969686518186626473348771189789580881377863614088	99	UVM_INFO @ 6608125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	52492852525437553092052739606144003398077872645292933149208976911926818756150	99	UVM_INFO @ 3331121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	102542344619838070471523504260864823231305168628119205341797959102563601358330	99	UVM_INFO @ 5827703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	63354098011706135342254380023841619308621397975110534999481194049506726341430	99	UVM_INFO @ 10283828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	104666367737225443557823390319520227648140984843748943426462183595149052139448	99	UVM_INFO @ 11076668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	113372890685259320889372094128265910917845071889595924401316494594776566315124	99	UVM_INFO @ 1142957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	97024919831001834152630957237758411539164728262483024466064099159978605690097	99	UVM_INFO @ 1276699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	108683460082267140294509236863329385890051460476698931819185166688071108743944	99	UVM_INFO @ 1385585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				6 test runs
	csrng_stress_all_with_rand_reset	27578138558287432140061331602263775863402111267981736250973210834607073409575	None
	csrng_stress_all_with_rand_reset	101231928161981929413855820799377794203162135398192453333316248087636127572380	None
	csrng_stress_all_with_rand_reset	43809850863902227601137257468388690836922475928511052619619171668218227465622	None
	csrng_stress_all_with_rand_reset	114453282319227893056764093615158176242830833396098253695968061932649735232800	None
	csrng_stress_all_with_rand_reset	55561100197575936582527339919500218163152559136902918971899253371367300972855	None
	csrng_stress_all_with_rand_reset	28252528570092715996707728491445022377671656268376750428456429470342360660589	None
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started				3 test runs
	csrng_stress_all_with_rand_reset	3236945894577559517631780742629700755637488745705713479196275405671304189825	141	UVM_INFO @ 729486309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	48115861251144155004370136035196813892925723580778964475601007940875244420613	124	UVM_INFO @ 615336658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	83079884973781486755483618537289487152954797345156386109376368690431408253091	107	UVM_INFO @ 32302901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq				2 test runs
	csrng_stress_all_with_rand_reset	86706589178819093321500917434066126416630019575118792945697986184841201030107	143	UVM_INFO @ 1132414796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	30616274967682490427370219403173203827440680495634241881456688377368103890475	125	UVM_INFO @ 4295473234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE				2 test runs
	csrng_regwen	10421861550172879704188873006693511913174794711710002632986445564471908701644	99	UVM_INFO @ 14436745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	63393219465660488082114444101895799509827584528165787355747838920267685072571	99	UVM_INFO @ 6849881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: csrng_reg_block.genbits				1 test run
	csrng_cmds	28080745660360031557544999751541825806852160063879165729837230653387566939524	113	UVM_INFO @ 664996800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert recov_alert triggered unexpectedly				1 test run
	csrng_cmds	10795600690806846262419211423444743823391038120742518911420741383943900220561	108	UVM_INFO @ 12807588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---