Simulation Results: edn/edn0

 
27/06/2026 02:42:03 DVSim: v1.49.0 sha: 1134d70 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.84 %
  • code
  • 95.74 %
  • assert
  • 98.92 %
  • func
  • 92.86 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.20 %
  • toggle
  • 97.12 %
  • FSM
  • 91.94 %
Validation stages
V1
100.00%
V2
98.68%
V2S
100.00%
V3
93.33%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.250s 21.225us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.090s 27.101us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.120s 16.761us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.620s 273.486us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.320s 55.071us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.490s 99.508us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.120s 16.761us 5 5 100.00
edn_csr_aliasing 1.320s 55.071us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 6.210s 809.247us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 6.210s 809.247us 100 100 100.00
genbits 100 100 100.00
edn_genbits 6.210s 809.247us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.270s 22.587us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.890s 297.449us 200 200 100.00
errs 100 100 100.00
edn_err 1.610s 21.269us 100 100 100.00
disable 92 100 92.00
edn_disable 1.280s 12.424us 50 50 100.00
edn_disable_auto_req_mode 13.300s 500.000us 42 50 84.00
stress_all 30 30 100.00
edn_stress_all 8.730s 543.014us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.070s 48.207us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.120s 25.799us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.600s 161.279us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.600s 161.279us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.090s 27.101us 1 1 100.00
edn_csr_rw 1.120s 16.761us 5 5 100.00
edn_csr_aliasing 1.320s 55.071us 1 1 100.00
edn_same_csr_outstanding 1.270s 61.404us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.090s 27.101us 1 1 100.00
edn_csr_rw 1.120s 16.761us 5 5 100.00
edn_csr_aliasing 1.320s 55.071us 1 1 100.00
edn_same_csr_outstanding 1.270s 61.404us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 7.160s 1070.690us 5 5 100.00
edn_tl_intg_err 5.250s 349.467us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.130s 16.317us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.890s 297.449us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.160s 1070.690us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.160s 1070.690us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 7.160s 1070.690us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 7.160s 1070.690us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.890s 297.449us 200 200 100.00
edn_sec_cm 7.160s 1070.690us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.890s 297.449us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 5.250s 349.467us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 28 30 93.33
edn_stress_all_with_rand_reset 99.820s 5505.658us 28 30 93.33

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 6 test runs
edn_disable_auto_req_mode 76933171582141264909605044932071846568219827738850558780032779951217337384676 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 66114672326990561515030505060199267095739328227619955306911968856568828254908 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 112706019992389035650620631961692234858503336148508332158226150042141788245488 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 84208642864569477465248416474594155026391998800665309759098380781104328850797 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 84447780292273196802063030630360909485575499579357323265528651488154757791826 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 109804872787637461820480142525545180179962198629206341731840917428191916776094 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
edn_stress_all_with_rand_reset 87633465163538581122116446461558233344793555809130741343168562894897203797183 155
UVM_INFO @ 474338590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 11951245377314336085013522257959828208859789902532577669522878304507466523632 172
UVM_INFO @ 1544644029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 2 test runs
edn_disable_auto_req_mode 68985589516112177156164362959737749418149479641826382886957729015005269103251 88
UVM_INFO @ 61732238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 97828411582775376803339836765614224172738175661223614384866505572712576930134 88
UVM_INFO @ 238792887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---