Simulation Results: edn/edn1

 
27/06/2026 02:42:03 DVSim: v1.49.0 sha: 1134d70 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.67 %
  • code
  • 95.66 %
  • assert
  • 98.70 %
  • func
  • 92.65 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.77 %
  • toggle
  • 96.15 %
  • FSM
  • 94.32 %
Validation stages
V1
100.00%
V2
98.52%
V2S
100.00%
V3
86.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.030s 27.911us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.740s 27.772us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.040s 19.248us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.550s 318.447us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.200s 145.865us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.190s 95.905us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.040s 19.248us 5 5 100.00
edn_csr_aliasing 1.200s 145.865us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 65.440s 4555.565us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 65.440s 4555.565us 100 100 100.00
genbits 100 100 100.00
edn_genbits 65.440s 4555.565us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.290s 29.789us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.630s 33.914us 200 200 100.00
errs 100 100 100.00
edn_err 1.460s 27.071us 100 100 100.00
disable 91 100 91.00
edn_disable 1.110s 32.027us 50 50 100.00
edn_disable_auto_req_mode 12.060s 500.000us 41 50 82.00
stress_all 30 30 100.00
edn_stress_all 6.440s 367.490us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.020s 27.890us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 0.980s 20.954us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.000s 430.686us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.000s 430.686us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 0.740s 27.772us 1 1 100.00
edn_csr_rw 1.040s 19.248us 5 5 100.00
edn_csr_aliasing 1.200s 145.865us 1 1 100.00
edn_same_csr_outstanding 1.160s 34.428us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 0.740s 27.772us 1 1 100.00
edn_csr_rw 1.040s 19.248us 5 5 100.00
edn_csr_aliasing 1.200s 145.865us 1 1 100.00
edn_same_csr_outstanding 1.160s 34.428us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 8.620s 911.177us 5 5 100.00
edn_tl_intg_err 3.620s 284.895us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.030s 19.247us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.630s 33.914us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 8.620s 911.177us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 8.620s 911.177us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 8.620s 911.177us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 8.620s 911.177us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.630s 33.914us 200 200 100.00
edn_sec_cm 8.620s 911.177us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.630s 33.914us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 3.620s 284.895us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 26 30 86.67
edn_stress_all_with_rand_reset 115.270s 26308.821us 26 30 86.67

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 5 test runs
edn_disable_auto_req_mode 3348430694967376463233170412523863365098249198573998507894186769209896152751 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 30120479701491412470585260599174607206954377679989270237206746014796323549211 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 47205859640576235281169120120453598639669826947804352779163233979387959457162 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 40499369518525271231982922499370553672134381331719711058138169254222668136742 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 68234932747189622570217290959470077767096173370470463282717693240068878571048 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
edn_stress_all_with_rand_reset 113358324949510960595906874138220999442734571887636548799194994093783775932801 231
UVM_INFO @ 1983363985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 47402899200113676862504419573260066088461958056379325565939418011030468779303 333
UVM_INFO @ 3910837006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 16301839815773018024883626135674981685638626603828318760241143230593652567253 134
UVM_INFO @ 137136331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 3 test runs
edn_disable_auto_req_mode 18671563342045695891496630534686191977670850011689972365218499746932307574313 88
UVM_INFO @ 45288283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 19212339177918598541118752835192654399177620337294624841438143738655500343590 88
UVM_INFO @ 69659991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 66895946096201902432689519824007052548172692710554502305292675594979465670760 88
UVM_INFO @ 121957871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit 1 test run
edn_stress_all_with_rand_reset 60356256484906304885083521616514153443064237430943791538575447420309672359866 135
/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 757086036 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup
UVM_FATAL (edn_scoreboard.sv:579) [scoreboard] Check failed (reqs_between_reseeds_ctr < max_num_reqs_between_reseeds) Maximum number of request between reseeds in auto_req_mode * exceeded. 1 test run
edn_disable_auto_req_mode 82097450690884510997065788173954926837579840448963284045681137675810313184099 90
UVM_INFO @ 58157368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---