Simulation Results

Simulation Results: flash_ctrl

27/06/2026 02:42:03 DVSim: v1.49.0 sha: 1134d70 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
97.07 %

code
95.78 %

assert
97.02 %

func
98.42 %

line
96.10 %

branch
97.42 %

cond
94.90 %

toggle
98.66 %

FSM
91.84 %

Validation stages

V1		100.00%
V2		98.61%
V2S		97.89%
V3		100.00%
unmapped		100.00%

70/70 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	flash_ctrl_smoke	180.910s	83.680us	50	50	100.00
smoke_hw				5	5	100.00
	flash_ctrl_smoke_hw	20.680s	32.428us	5	5	100.00
csr_hw_reset				1	1	100.00
	flash_ctrl_csr_hw_reset	13.110s	32.117us	1	1	100.00
csr_rw				5	5	100.00
	flash_ctrl_csr_rw	16.030s	314.242us	5	5	100.00
csr_bit_bash				1	1	100.00
	flash_ctrl_csr_bit_bash	56.300s	3317.236us	1	1	100.00
csr_aliasing				1	1	100.00
	flash_ctrl_csr_aliasing	33.540s	429.399us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	flash_ctrl_csr_mem_rw_with_rand_reset	19.760s	30.754us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	flash_ctrl_csr_rw	16.030s	314.242us	5	5	100.00
	flash_ctrl_csr_aliasing	33.540s	429.399us	1	1	100.00
mem_walk				1	1	100.00
	flash_ctrl_mem_walk	9.000s	56.234us	1	1	100.00
mem_partial_access				1	1	100.00
	flash_ctrl_mem_partial_access	11.800s	20.349us	1	1	100.00

922/935 passed

98.61 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sw_op				5	5	100.00
	flash_ctrl_sw_op	22.130s	77.801us	5	5	100.00
host_read_direct				5	5	100.00
	flash_ctrl_host_dir_rd	85.220s	78.563us	5	5	100.00
rma_hw_if				43	43	100.00
	flash_ctrl_hw_rma	1612.380s	136867.282us	3	3	100.00
	flash_ctrl_hw_rma_reset	991.860s	630382.531us	20	20	100.00
	flash_ctrl_lcmgr_intg	14.540s	97.671us	20	20	100.00
host_controller_arb				5	5	100.00
	flash_ctrl_host_ctrl_arb	1919.520s	286310.590us	5	5	100.00
erase_suspend				5	5	100.00
	flash_ctrl_erase_suspend	268.670s	8559.247us	5	5	100.00
program_reset				29	30	96.67
	flash_ctrl_prog_reset	3604.012s	0.000us	29	30	96.67
full_memory_access				5	5	100.00
	flash_ctrl_full_mem_access	3278.630s	417202.570us	5	5	100.00
rd_buff_eviction				5	5	100.00
	flash_ctrl_rd_buff_evict	97.200s	2090.097us	5	5	100.00
rd_buff_eviction_w_ecc				102	105	97.14
	flash_ctrl_rw_evict	34.670s	31.035us	37	40	92.50
	flash_ctrl_rw_evict_all_en	33.810s	32.634us	40	40	100.00
	flash_ctrl_re_evict	34.550s	72.528us	25	25	100.00
host_arb				20	20	100.00
	flash_ctrl_phy_arb	343.410s	4014.913us	20	20	100.00
host_interleave				20	20	100.00
	flash_ctrl_phy_arb	343.410s	4014.913us	20	20	100.00
memory_protection				20	20	100.00
	flash_ctrl_mp_regions	515.120s	11786.251us	20	20	100.00
fetch_code				10	10	100.00
	flash_ctrl_fetch_code	33.410s	1223.607us	10	10	100.00
all_partitions				20	20	100.00
	flash_ctrl_rand_ops	694.810s	8785.220us	20	20	100.00
error_mp				10	10	100.00
	flash_ctrl_error_mp	655.790s	5079.076us	10	10	100.00
error_prog_win				10	10	100.00
	flash_ctrl_error_prog_win	543.680s	1153.068us	10	10	100.00
error_prog_type				5	5	100.00
	flash_ctrl_error_prog_type	1645.540s	2517.727us	5	5	100.00
error_read_seed				20	20	100.00
	flash_ctrl_hw_read_seed_err	14.510s	24.262us	20	20	100.00
read_write_overflow				5	5	100.00
	flash_ctrl_oversize_error	134.820s	6755.644us	5	5	100.00
flash_ctrl_disable				50	50	100.00
	flash_ctrl_disable	24.670s	254.736us	50	50	100.00
flash_ctrl_connect				80	80	100.00
	flash_ctrl_connect	18.300s	16.092us	80	80	100.00
stress_all				5	5	100.00
	flash_ctrl_stress_all	920.440s	259.908us	5	5	100.00
secret_partition				127	130	97.69
	flash_ctrl_hw_sec_otp	192.980s	22251.850us	50	50	100.00
	flash_ctrl_otp_reset	117.510s	78.983us	77	80	96.25
isolation_partition				3	3	100.00
	flash_ctrl_hw_rma	1612.380s	136867.282us	3	3	100.00
interrupts				98	100	98.00
	flash_ctrl_intr_rd	186.470s	3786.887us	38	40	95.00
	flash_ctrl_intr_wr	73.550s	5203.675us	10	10	100.00
	flash_ctrl_intr_rd_slow_flash	378.710s	17623.793us	40	40	100.00
	flash_ctrl_intr_wr_slow_flash	234.170s	58785.786us	10	10	100.00
invalid_op				20	20	100.00
	flash_ctrl_invalid_op	73.770s	4017.621us	20	20	100.00
mid_op_rst				5	5	100.00
	flash_ctrl_mid_op_rst	64.130s	3952.223us	5	5	100.00
double_bit_err				34	35	97.14
	flash_ctrl_read_word_sweep_derr	20.670s	52.338us	5	5	100.00
	flash_ctrl_ro_derr	135.860s	1836.159us	10	10	100.00
	flash_ctrl_rw_derr	191.260s	12422.858us	10	10	100.00
	flash_ctrl_derr_detect	162.030s	5912.363us	4	5	80.00
	flash_ctrl_integrity	467.060s	66528.666us	5	5	100.00
single_bit_err				25	25	100.00
	flash_ctrl_read_word_sweep_serr	23.320s	70.978us	5	5	100.00
	flash_ctrl_ro_serr	135.390s	3618.189us	10	10	100.00
	flash_ctrl_rw_serr	179.700s	5766.259us	10	10	100.00
singlebit_err_counter				5	5	100.00
	flash_ctrl_serr_counter	76.390s	6803.583us	5	5	100.00
singlebit_err_address				5	5	100.00
	flash_ctrl_serr_address	78.170s	1064.824us	5	5	100.00
scramble				59	62	95.16
	flash_ctrl_wo	3604.012s	0.000us	19	20	95.00
	flash_ctrl_write_word_sweep	14.210s	44.241us	1	1	100.00
	flash_ctrl_read_word_sweep	13.220s	146.287us	1	1	100.00
	flash_ctrl_ro	111.650s	752.492us	20	20	100.00
	flash_ctrl_rw	3604.010s	0.000us	18	20	90.00
filesystem_support				5	5	100.00
	flash_ctrl_fs_sup	34.790s	2098.710us	5	5	100.00
rma_write_process_error				23	23	100.00
	flash_ctrl_rma_err	703.520s	103687.328us	3	3	100.00
	flash_ctrl_hw_prog_rma_wipe_err	123.330s	10034.397us	20	20	100.00
alert_test				10	10	100.00
	flash_ctrl_alert_test	14.360s	146.149us	10	10	100.00
intr_test				10	10	100.00
	flash_ctrl_intr_test	14.180s	62.319us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	flash_ctrl_tl_errors	20.050s	237.283us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	flash_ctrl_tl_errors	20.050s	237.283us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	flash_ctrl_csr_hw_reset	13.110s	32.117us	1	1	100.00
	flash_ctrl_csr_rw	16.030s	314.242us	5	5	100.00
	flash_ctrl_csr_aliasing	33.540s	429.399us	1	1	100.00
	flash_ctrl_same_csr_outstanding	18.380s	70.724us	5	5	100.00
tl_d_partial_access				12	12	100.00
	flash_ctrl_csr_hw_reset	13.110s	32.117us	1	1	100.00
	flash_ctrl_csr_rw	16.030s	314.242us	5	5	100.00
	flash_ctrl_csr_aliasing	33.540s	429.399us	1	1	100.00
	flash_ctrl_same_csr_outstanding	18.380s	70.724us	5	5	100.00

V2S

465/475 passed

97.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	74.180s	67.439us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	flash_ctrl_shadow_reg_errors	74.180s	67.439us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	74.180s	67.439us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	flash_ctrl_shadow_reg_errors	74.180s	67.439us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	flash_ctrl_shadow_reg_errors_with_csr_rw	84.410s	359.807us	20	20	100.00
tl_intg_err				28	30	93.33
	flash_ctrl_sec_cm	2435.440s	21225.945us	3	5	60.00
	flash_ctrl_tl_intg_err	670.120s	1661.009us	25	25	100.00
sec_cm_reg_bus_integrity				25	25	100.00
	flash_ctrl_tl_intg_err	670.120s	1661.009us	25	25	100.00
sec_cm_host_bus_integrity				25	25	100.00
	flash_ctrl_tl_intg_err	670.120s	1661.009us	25	25	100.00
sec_cm_mem_bus_integrity				6	6	100.00
	flash_ctrl_rd_intg	20.340s	238.492us	3	3	100.00
	flash_ctrl_wr_intg	15.580s	182.729us	3	3	100.00
sec_cm_scramble_key_sideload				50	50	100.00
	flash_ctrl_smoke	180.910s	83.680us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				257	260	98.85
	flash_ctrl_otp_reset	117.510s	78.983us	77	80	96.25
	flash_ctrl_disable	24.670s	254.736us	50	50	100.00
	flash_ctrl_sec_info_access	104.760s	34693.086us	50	50	100.00
	flash_ctrl_connect	18.300s	16.092us	80	80	100.00
sec_cm_ctrl_config_regwen				5	5	100.00
	flash_ctrl_config_regwen	15.040s	201.181us	5	5	100.00
sec_cm_data_regions_config_regwen				5	5	100.00
	flash_ctrl_csr_rw	16.030s	314.242us	5	5	100.00
sec_cm_data_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	74.180s	67.439us	20	20	100.00
sec_cm_info_regions_config_regwen				5	5	100.00
	flash_ctrl_csr_rw	16.030s	314.242us	5	5	100.00
sec_cm_info_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	74.180s	67.439us	20	20	100.00
sec_cm_bank_config_regwen				5	5	100.00
	flash_ctrl_csr_rw	16.030s	314.242us	5	5	100.00
sec_cm_bank_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	74.180s	67.439us	20	20	100.00
sec_cm_mem_ctrl_global_esc				50	50	100.00
	flash_ctrl_disable	24.670s	254.736us	50	50	100.00
sec_cm_mem_ctrl_local_esc				6	6	100.00
	flash_ctrl_rd_intg	20.340s	238.492us	3	3	100.00
	flash_ctrl_access_after_disable	12.680s	306.550us	3	3	100.00
sec_cm_mem_addr_infection				3	3	100.00
	flash_ctrl_host_addr_infection	30.080s	41.769us	3	3	100.00
sec_cm_mem_disable_config_mubi				50	50	100.00
	flash_ctrl_disable	24.670s	254.736us	50	50	100.00
sec_cm_exec_config_redun				10	10	100.00
	flash_ctrl_fetch_code	33.410s	1223.607us	10	10	100.00
sec_cm_mem_scramble				18	20	90.00
	flash_ctrl_rw	3604.010s	0.000us	18	20	90.00
sec_cm_mem_integrity				25	25	100.00
	flash_ctrl_rw_serr	179.700s	5766.259us	10	10	100.00
	flash_ctrl_rw_derr	191.260s	12422.858us	10	10	100.00
	flash_ctrl_integrity	467.060s	66528.666us	5	5	100.00
sec_cm_rma_entry_mem_sec_wipe				3	3	100.00
	flash_ctrl_hw_rma	1612.380s	136867.282us	3	3	100.00
sec_cm_ctrl_fsm_sparse				3	5	60.00
	flash_ctrl_sec_cm	2435.440s	21225.945us	3	5	60.00
sec_cm_phy_fsm_sparse				3	5	60.00
	flash_ctrl_sec_cm	2435.440s	21225.945us	3	5	60.00
sec_cm_phy_prog_fsm_sparse				3	5	60.00
	flash_ctrl_sec_cm	2435.440s	21225.945us	3	5	60.00
sec_cm_ctr_redun				3	5	60.00
	flash_ctrl_sec_cm	2435.440s	21225.945us	3	5	60.00
sec_cm_phy_arbiter_ctrl_redun				5	5	100.00
	flash_ctrl_phy_arb_redun	18.500s	878.382us	5	5	100.00
sec_cm_phy_host_grant_ctrl_consistency				3	5	60.00
	flash_ctrl_phy_host_grant_err	12.640s	104.391us	3	5	60.00
sec_cm_phy_ack_ctrl_consistency				4	5	80.00
	flash_ctrl_phy_ack_consistency	15.230s	427.523us	4	5	80.00
sec_cm_fifo_ctr_redun				3	5	60.00
	flash_ctrl_sec_cm	2435.440s	21225.945us	3	5	60.00
sec_cm_mem_tl_lc_gate_fsm_sparse				3	5	60.00
	flash_ctrl_sec_cm	2435.440s	21225.945us	3	5	60.00
sec_cm_prog_tl_lc_gate_fsm_sparse				3	5	60.00
	flash_ctrl_sec_cm	2435.440s	21225.945us	3	5	60.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
asymmetric_read_path				1	1	100.00
	flash_ctrl_rd_ooo	40.920s	110.732us	1	1	100.00

unmapped

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				3	3	100.00
	flash_ctrl_basic_rw	597.430s	1136.971us	3	3	100.00

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				4 test runs
	flash_ctrl_prog_reset	105700257477283426386040954581100222303777327542793136409533961325849568975081	None
	flash_ctrl_wo	113583514811648544581509960737982135518698570747771098780956997689702979082750	None
	flash_ctrl_rw	51489209388280561291099137344599923535800374370030357113299050012340808099322	None
	flash_ctrl_rw	90762642981780051177279922296773498456234379702242409699666109316608960815729	None
Offending 'dst_req_o'				3 test runs
	flash_ctrl_otp_reset	39171794864510201032235086250513194021675324358064020720981026894544634515792	213	UVM_ERROR @ 45604.8 ns: (prim_sync_reqack.sv:355) [ASSERT FAILED] SyncReqAckAckNeedsReq UVM_INFO @ 45604.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_otp_reset	13595520548826266550511998713939423412368533836742853956811875777197254845728	185	UVM_ERROR @ 17042.7 ns: (prim_sync_reqack.sv:355) [ASSERT FAILED] SyncReqAckAckNeedsReq UVM_INFO @ 17042.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_otp_reset	5251421971545849823914087238767205636454465993412219447770902115633892360648	124	UVM_ERROR @ 3445.7 ns: (prim_sync_reqack.sv:355) [ASSERT FAILED] SyncReqAckAckNeedsReq UVM_INFO @ 3445.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'				2 test runs
	flash_ctrl_phy_host_grant_err	79038401977172751816435244238517748966706391777135872573180764214682746648175	125	UVM_ERROR @ 22693.6 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 22693.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_phy_host_grant_err	13157176324524297993465770254236629071692641022097183649179223551179652930526	125	UVM_ERROR @ 23066.9 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 23066.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (alert_receiver_driver.sv:262) driver [driver] m_transaction_tasks nonempty after reset: '{:}				2 test runs
	flash_ctrl_sec_cm	106682914358056825260558792724861792144221606947957078206290353633960424593770	2007	UVM_INFO @ 378159.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_sec_cm	41042905466727023333943548143480403150493647162346804773093848823492353438529	6491	UVM_INFO @ 877094.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.op_status.err reset value:				2 test runs
	flash_ctrl_rw_evict	93332460937177751066830831725744103791929853668297719868136637798849274554733	108	UVM_INFO @ 29641.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict	112329071003128961412860177026299214225997268336699086627059240109991068223980	108	UVM_INFO @ 23053.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_std_err did not trigger max_delay:*				1 test run
	flash_ctrl_phy_ack_consistency	63710002437798469657468601213763898525214793210763170596874787591638412926677	109	UVM_INFO @ 427523.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert fatal_err triggered unexpectedly				1 test run
	flash_ctrl_derr_detect	108164801363938601273456164380573160918578771099199996399253163814963048261634	119	UVM_INFO @ 35343.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp fed08a7f_4fe5bf0b:ffffffff_4fe5bf0b mismatch!!				1 test run
	flash_ctrl_intr_rd	40270866731331786852100788205336931471896735932204058527851116254974872773262	108	UVM_INFO @ 3661336.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp b7aefd91_943ccb01:ffffffff_943ccb mismatch!!				1 test run
	flash_ctrl_intr_rd	7033661117857160210235646943038241748625528155944771900827675262425367217480	108	UVM_INFO @ 4172939.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value:				1 test run
	flash_ctrl_rw_evict	38409285048979088538343847441927225856002127431811867960989090865763284936278	108	UVM_INFO @ 13256.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---