Simulation Results: hmac

 
27/06/2026 02:42:03 DVSim: v1.49.0 sha: 1134d70 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.82 %
  • code
  • 99.19 %
  • assert
  • 97.60 %
  • func
  • 99.68 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.52 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 11.480s 4195.240us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 138.013us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.270s 126.134us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 6.160s 574.994us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.580s 105.389us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 296.280s 27987.268us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.270s 126.134us 5 5 100.00
hmac_csr_aliasing 4.580s 105.389us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 134.750s 13647.776us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 93.180s 4934.903us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 271.190s 43043.289us 30 30 100.00
hmac_test_sha384_vectors 549.670s 40932.149us 75 75 100.00
hmac_test_sha512_vectors 541.780s 25598.457us 75 75 100.00
hmac_test_hmac256_vectors 15.650s 1557.741us 50 50 100.00
hmac_test_hmac384_vectors 18.500s 2266.397us 60 60 100.00
hmac_test_hmac512_vectors 19.080s 3533.998us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 42.200s 4246.023us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1319.560s 39683.429us 10 10 100.00
error 10 10 100.00
hmac_error 102.460s 3081.890us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 108.320s 100761.560us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 11.480s 4195.240us 10 10 100.00
hmac_long_msg 134.750s 13647.776us 10 10 100.00
hmac_back_pressure 93.180s 4934.903us 25 25 100.00
hmac_datapath_stress 1319.560s 39683.429us 10 10 100.00
hmac_burst_wr 42.200s 4246.023us 50 50 100.00
hmac_stress_all 2033.260s 245666.886us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 11.480s 4195.240us 10 10 100.00
hmac_long_msg 134.750s 13647.776us 10 10 100.00
hmac_back_pressure 93.180s 4934.903us 25 25 100.00
hmac_datapath_stress 1319.560s 39683.429us 10 10 100.00
hmac_wipe_secret 108.320s 100761.560us 10 10 100.00
hmac_test_sha256_vectors 271.190s 43043.289us 30 30 100.00
hmac_test_sha384_vectors 549.670s 40932.149us 75 75 100.00
hmac_test_sha512_vectors 541.780s 25598.457us 75 75 100.00
hmac_test_hmac256_vectors 15.650s 1557.741us 50 50 100.00
hmac_test_hmac384_vectors 18.500s 2266.397us 60 60 100.00
hmac_test_hmac512_vectors 19.080s 3533.998us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 11.480s 4195.240us 10 10 100.00
hmac_long_msg 134.750s 13647.776us 10 10 100.00
hmac_back_pressure 93.180s 4934.903us 25 25 100.00
hmac_datapath_stress 1319.560s 39683.429us 10 10 100.00
hmac_burst_wr 42.200s 4246.023us 50 50 100.00
hmac_error 102.460s 3081.890us 10 10 100.00
hmac_wipe_secret 108.320s 100761.560us 10 10 100.00
hmac_test_sha256_vectors 271.190s 43043.289us 30 30 100.00
hmac_test_sha384_vectors 549.670s 40932.149us 75 75 100.00
hmac_test_sha512_vectors 541.780s 25598.457us 75 75 100.00
hmac_test_hmac256_vectors 15.650s 1557.741us 50 50 100.00
hmac_test_hmac384_vectors 18.500s 2266.397us 60 60 100.00
hmac_test_hmac512_vectors 19.080s 3533.998us 75 75 100.00
hmac_stress_all 2033.260s 245666.886us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2033.260s 245666.886us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 0.930s 33.796us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 0.960s 71.897us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 3.850s 810.611us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 3.850s 810.611us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 1.000s 138.013us 1 1 100.00
hmac_csr_rw 1.270s 126.134us 5 5 100.00
hmac_csr_aliasing 4.580s 105.389us 1 1 100.00
hmac_same_csr_outstanding 2.240s 150.199us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 1.000s 138.013us 1 1 100.00
hmac_csr_rw 1.270s 126.134us 5 5 100.00
hmac_csr_aliasing 4.580s 105.389us 1 1 100.00
hmac_same_csr_outstanding 2.240s 150.199us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 1.200s 119.654us 5 5 100.00
hmac_tl_intg_err 4.840s 250.785us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 4.840s 250.785us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 11.480s 4195.240us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 7.610s 142.693us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 562.110s 20291.784us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.530s 172.460us 1 1 100.00