Simulation Results: keymgr

 
27/06/2026 02:42:03 DVSim: v1.49.0 sha: 1134d70 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.89 %
  • code
  • 98.83 %
  • assert
  • 97.72 %
  • func
  • 91.11 %
  • line
  • 99.20 %
  • branch
  • 99.09 %
  • cond
  • 98.16 %
  • toggle
  • 97.72 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.06%
V2S
99.69%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 30 30 100.00
keymgr_smoke 23.820s 3296.654us 30 30 100.00
random 30 30 100.00
keymgr_random 38.530s 1455.031us 30 30 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.260s 18.298us 1 1 100.00
csr_rw 5 5 100.00
keymgr_csr_rw 1.380s 32.516us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 7.510s 720.645us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 8.650s 1476.140us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_csr_mem_rw_with_rand_reset 2.260s 129.984us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_csr_rw 1.380s 32.516us 5 5 100.00
keymgr_csr_aliasing 8.650s 1476.140us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 73.430s 2144.690us 50 50 100.00
sideload 80 80 100.00
keymgr_sideload 18.750s 809.690us 20 20 100.00
keymgr_sideload_kmac 39.060s 5614.444us 20 20 100.00
keymgr_sideload_aes 17.490s 3209.417us 20 20 100.00
keymgr_sideload_otbn 15.250s 931.448us 20 20 100.00
direct_to_disabled_state 30 30 100.00
keymgr_direct_to_disabled 11.460s 2452.074us 30 30 100.00
lc_disable 49 50 98.00
keymgr_lc_disable 19.380s 3831.383us 49 50 98.00
kmac_error_response 20 20 100.00
keymgr_kmac_rsp_err 5.240s 510.998us 20 20 100.00
invalid_sw_input 20 20 100.00
keymgr_sw_invalid_input 47.570s 2206.427us 20 20 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 46.550s 28820.910us 50 50 100.00
sync_async_fault_cross 20 20 100.00
keymgr_sync_async_fault_cross 14.210s 2460.445us 20 20 100.00
stress_all 47 50 94.00
keymgr_stress_all 436.000s 24922.154us 47 50 94.00
intr_test 10 10 100.00
keymgr_intr_test 1.080s 21.077us 10 10 100.00
alert_test 10 10 100.00
keymgr_alert_test 1.150s 17.133us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_tl_errors 3.830s 544.947us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_tl_errors 3.830s 544.947us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_csr_hw_reset 1.260s 18.298us 1 1 100.00
keymgr_csr_rw 1.380s 32.516us 5 5 100.00
keymgr_csr_aliasing 8.650s 1476.140us 1 1 100.00
keymgr_same_csr_outstanding 2.640s 289.298us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_csr_hw_reset 1.260s 18.298us 1 1 100.00
keymgr_csr_rw 1.380s 32.516us 5 5 100.00
keymgr_csr_aliasing 8.650s 1476.140us 1 1 100.00
keymgr_same_csr_outstanding 2.640s 289.298us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 11.200s 4805.465us 5 5 100.00
tl_intg_err 30 30 100.00
keymgr_sec_cm 11.200s 4805.465us 5 5 100.00
keymgr_tl_intg_err 9.490s 463.687us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 6.240s 832.517us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 6.240s 832.517us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 6.240s 832.517us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 6.240s 832.517us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 17.490s 745.797us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 11.200s 4805.465us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 11.200s 4805.465us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
keymgr_tl_intg_err 9.490s 463.687us 25 25 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 6.240s 832.517us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 73.430s 2144.690us 50 50 100.00
sec_cm_reseed_config_regwen 35 35 100.00
keymgr_random 38.530s 1455.031us 30 30 100.00
keymgr_csr_rw 1.380s 32.516us 5 5 100.00
sec_cm_sw_binding_config_regwen 35 35 100.00
keymgr_random 38.530s 1455.031us 30 30 100.00
keymgr_csr_rw 1.380s 32.516us 5 5 100.00
sec_cm_max_key_ver_config_regwen 35 35 100.00
keymgr_random 38.530s 1455.031us 30 30 100.00
keymgr_csr_rw 1.380s 32.516us 5 5 100.00
sec_cm_lc_ctrl_intersig_mubi 49 50 98.00
keymgr_lc_disable 19.380s 3831.383us 49 50 98.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 46.550s 28820.910us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 46.550s 28820.910us 50 50 100.00
sec_cm_hw_key_sw_noaccess 30 30 100.00
keymgr_random 38.530s 1455.031us 30 30 100.00
sec_cm_output_keys_ctrl_redun 20 20 100.00
keymgr_sideload_protect 37.770s 21642.202us 20 20 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 11.200s 4805.465us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 11.200s 4805.465us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 11.200s 4805.465us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 34.110s 4538.936us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 49 50 98.00
keymgr_lc_disable 19.380s 3831.383us 49 50 98.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 11.200s 4805.465us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 11.200s 4805.465us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 11.200s 4805.465us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 34.110s 4538.936us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 34.110s 4538.936us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 11.200s 4805.465us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 34.110s 4538.936us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 11.200s 4805.465us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 34.110s 4538.936us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 20 40.00
keymgr_stress_all_with_rand_reset 20.110s 2523.410us 8 20 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 12 test runs
keymgr_stress_all_with_rand_reset 25142204176635103846872349063091566208256513058483927969620923480499220554000 198
UVM_INFO @ 212121801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 9420207264483855058936925454940978051194483152124676262687366130698187515668 315
UVM_INFO @ 488864587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 80130765770182573147952564129143751878391998543514970431114220962142640456578 463
UVM_INFO @ 164367542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 111569634148914817517774886231367309540704844294867112582054189363013333168642 353
UVM_INFO @ 755820483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 47595132872717583447538676486283000035424848507612808237581468694074622316547 165
UVM_INFO @ 2040235058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 66090404041352161184882430308290512130555459851968937777939920702818694539347 383
UVM_INFO @ 217544765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 61812013182746428672496302056361649363568087884221287350593684316078000782440 184
UVM_INFO @ 120169847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 98963432559650815070743595237737001742136453585773065063908566327543858921893 817
UVM_INFO @ 665603877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 46857955554743570858912333213217188013623046802022048113754839879859379546789 152
UVM_INFO @ 109678082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 64443167376912524397755620448896058429599343749343792568801111185561914272625 102
UVM_INFO @ 405652744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 110848442128130498495661103253655857947307403594653176572051977175505575816238 193
UVM_INFO @ 211623836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 78047705500282329851815644913432902452391901683779343285351135466863892235497 142
UVM_INFO @ 532996509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_* 2 test runs
keymgr_lc_disable 107832637073924878792832839441546205416218467198393433214179827884091319169652 318
UVM_INFO @ 385798587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all 82576837840714329620982110111877515601368209301219374658716648075993418653689 268
UVM_INFO @ 64696256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* 1 test run
keymgr_stress_all 89104674317836447317943058678801123276823216531857933072461140156539314557792 966
UVM_INFO @ 798437522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_* 1 test run
keymgr_stress_all 107917715273416549453411373377316617270818888051773580937186515262728726875864 658
UVM_INFO @ 494382453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---