Simulation Results: lc_ctrl/volatile_unlock_disabled

 
27/06/2026 02:42:03 DVSim: v1.49.0 sha: 1134d70 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.36 %
  • code
  • 85.66 %
  • assert
  • 94.97 %
  • func
  • 96.44 %
  • line
  • 97.28 %
  • branch
  • 94.00 %
  • cond
  • 81.48 %
  • toggle
  • 88.25 %
  • FSM
  • 67.29 %
Validation stages
V1
100.00%
V2
99.06%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 5.480s 1039.465us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.280s 17.930us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.360s 14.309us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.730s 392.441us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.310s 39.949us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.450s 117.948us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.360s 14.309us 5 5 100.00
lc_ctrl_csr_aliasing 2.310s 39.949us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 9.380s 80.306us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 10.330s 257.201us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.360s 16.617us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.270s 93.155us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 12.970s 1106.847us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 16.540s 1119.790us 19 20 95.00
security_escalation 138 140 98.57
lc_ctrl_state_failure 12.970s 1106.847us 20 20 100.00
lc_ctrl_prog_failure 4.270s 93.155us 20 20 100.00
lc_ctrl_errors 16.540s 1119.790us 19 20 95.00
lc_ctrl_security_escalation 12.740s 1391.950us 20 20 100.00
lc_ctrl_jtag_state_failure 55.920s 2351.187us 20 20 100.00
lc_ctrl_jtag_prog_failure 14.110s 7384.787us 20 20 100.00
lc_ctrl_jtag_errors 87.580s 8725.759us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 9.180s 1048.113us 20 20 100.00
lc_ctrl_jtag_state_post_trans 23.340s 759.739us 20 20 100.00
lc_ctrl_jtag_prog_failure 14.110s 7384.787us 20 20 100.00
lc_ctrl_jtag_errors 87.580s 8725.759us 19 20 95.00
lc_ctrl_jtag_access 21.260s 4321.792us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 33.040s 2476.597us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.100s 159.515us 10 10 100.00
lc_ctrl_jtag_csr_rw 4.480s 309.750us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 17.440s 933.752us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 10.890s 979.712us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.260s 178.529us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.490s 439.301us 10 10 100.00
lc_ctrl_jtag_alert_test 1.980s 257.237us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 15.220s 4602.004us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.320s 15.426us 10 10 100.00
stress_all 8 10 80.00
lc_ctrl_stress_all 211.840s 8308.507us 8 10 80.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.610s 84.378us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.120s 368.679us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.120s 368.679us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.280s 17.930us 1 1 100.00
lc_ctrl_csr_rw 1.360s 14.309us 5 5 100.00
lc_ctrl_csr_aliasing 2.310s 39.949us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.360s 190.962us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.280s 17.930us 1 1 100.00
lc_ctrl_csr_rw 1.360s 14.309us 5 5 100.00
lc_ctrl_csr_aliasing 2.310s 39.949us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.360s 190.962us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 10.070s 2156.230us 5 5 100.00
lc_ctrl_tl_intg_err 3.640s 120.919us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.640s 120.919us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 10.330s 257.201us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 12.970s 1106.847us 20 20 100.00
lc_ctrl_sec_cm 10.070s 2156.230us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 12.970s 1106.847us 20 20 100.00
lc_ctrl_sec_cm 10.070s 2156.230us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 12.970s 1106.847us 20 20 100.00
lc_ctrl_sec_cm 10.070s 2156.230us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 12.970s 1106.847us 20 20 100.00
lc_ctrl_sec_cm 10.070s 2156.230us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 12.970s 1106.847us 20 20 100.00
lc_ctrl_sec_cm 10.070s 2156.230us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 12.970s 1106.847us 20 20 100.00
lc_ctrl_sec_cm 10.070s 2156.230us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 12.970s 1106.847us 20 20 100.00
lc_ctrl_sec_cm 10.070s 2156.230us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 12.970s 1106.847us 20 20 100.00
lc_ctrl_sec_cm 10.070s 2156.230us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 12.740s 1391.950us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 9.380s 80.306us 20 20 100.00
lc_ctrl_jtag_state_post_trans 23.340s 759.739us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 15.010s 1057.017us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 15.010s 1057.017us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 11.690s 677.867us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 12.240s 448.038us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 12.240s 448.038us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
lc_ctrl_stress_all_with_rand_reset 71.960s 11341.763us 5 10 50.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 4 test runs
lc_ctrl_jtag_errors 16939078576087331713912018877848370186948047909118116730028672188355495590486 3720
UVM_INFO @ 18820925952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 111982217570441765802329743696362634185736567924761858962671922238556638037426 1538
UVM_INFO @ 183261185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 40619306839673271513037073098113356985879788386697930735531510586512768731870 6266
UVM_INFO @ 13116672248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 103355220805562768751031222741894782865939951191272122259700087248388174815388 1547
UVM_INFO @ 132531682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 50071214061427497469760957638312783942175528099229887214470013517666398965811 3112
UVM_INFO @ 25555447187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 71084349262733647469768028918174885087264629891815115737904438298771473132954 151
UVM_INFO @ 149946626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 110112993665963071827044916073177071733648857035904758827573362293800746001102 939
UVM_INFO @ 531270832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 17035577589618486548810535318622485835435394613747656533283896439624076079941 4708
UVM_INFO @ 4679954883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_scoreboard.sv:248) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* 1 test run
lc_ctrl_stress_all_with_rand_reset 36722654692871846479237043943304787238323021289516692845607641426737963320689 623
UVM_INFO @ 654639366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---