Simulation Results: lc_ctrl/volatile_unlock_enabled

 
27/06/2026 02:42:03 DVSim: v1.49.0 sha: 1134d70 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.34 %
  • code
  • 85.90 %
  • assert
  • 94.69 %
  • func
  • 96.44 %
  • line
  • 97.26 %
  • branch
  • 94.09 %
  • cond
  • 81.69 %
  • toggle
  • 88.25 %
  • FSM
  • 68.22 %
Validation stages
V1
100.00%
V2
98.59%
V2S
100.00%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 8.660s 3803.738us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.250s 15.690us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.340s 68.369us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.020s 115.690us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.490s 27.487us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.160s 37.348us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.340s 68.369us 5 5 100.00
lc_ctrl_csr_aliasing 1.490s 27.487us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 10.390s 248.814us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 13.590s 1494.397us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.320s 14.560us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.340s 471.723us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 16.600s 2814.247us 20 20 100.00
lc_errors 17 20 85.00
lc_ctrl_errors 14.840s 6452.527us 17 20 85.00
security_escalation 135 140 96.43
lc_ctrl_state_failure 16.600s 2814.247us 20 20 100.00
lc_ctrl_prog_failure 4.340s 471.723us 20 20 100.00
lc_ctrl_errors 14.840s 6452.527us 17 20 85.00
lc_ctrl_security_escalation 11.270s 1785.753us 20 20 100.00
lc_ctrl_jtag_state_failure 65.820s 12654.225us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.550s 3515.123us 20 20 100.00
lc_ctrl_jtag_errors 44.950s 4640.822us 18 20 90.00
jtag_access 208 210 99.05
lc_ctrl_jtag_smoke 16.810s 2981.055us 20 20 100.00
lc_ctrl_jtag_state_post_trans 21.640s 1257.568us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.550s 3515.123us 20 20 100.00
lc_ctrl_jtag_errors 44.950s 4640.822us 18 20 90.00
lc_ctrl_jtag_access 22.140s 3535.743us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 27.180s 5007.580us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.210s 209.576us 10 10 100.00
lc_ctrl_jtag_csr_rw 4.630s 339.942us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 15.220s 1335.447us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 13.750s 4794.881us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.960s 164.130us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 7.900s 1655.278us 10 10 100.00
lc_ctrl_jtag_alert_test 2.470s 281.577us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 28.780s 1593.936us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.470s 29.900us 10 10 100.00
stress_all 9 10 90.00
lc_ctrl_stress_all 220.700s 15172.993us 9 10 90.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.650s 32.047us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.200s 187.077us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.200s 187.077us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.250s 15.690us 1 1 100.00
lc_ctrl_csr_rw 1.340s 68.369us 5 5 100.00
lc_ctrl_csr_aliasing 1.490s 27.487us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.060s 295.842us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.250s 15.690us 1 1 100.00
lc_ctrl_csr_rw 1.340s 68.369us 5 5 100.00
lc_ctrl_csr_aliasing 1.490s 27.487us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.060s 295.842us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 11.260s 1174.562us 5 5 100.00
lc_ctrl_tl_intg_err 4.000s 498.366us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.000s 498.366us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 13.590s 1494.397us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 16.600s 2814.247us 20 20 100.00
lc_ctrl_sec_cm 11.260s 1174.562us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 16.600s 2814.247us 20 20 100.00
lc_ctrl_sec_cm 11.260s 1174.562us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 16.600s 2814.247us 20 20 100.00
lc_ctrl_sec_cm 11.260s 1174.562us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 16.600s 2814.247us 20 20 100.00
lc_ctrl_sec_cm 11.260s 1174.562us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 16.600s 2814.247us 20 20 100.00
lc_ctrl_sec_cm 11.260s 1174.562us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 16.600s 2814.247us 20 20 100.00
lc_ctrl_sec_cm 11.260s 1174.562us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 16.600s 2814.247us 20 20 100.00
lc_ctrl_sec_cm 11.260s 1174.562us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 16.600s 2814.247us 20 20 100.00
lc_ctrl_sec_cm 11.260s 1174.562us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 11.270s 1785.753us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 10.390s 248.814us 20 20 100.00
lc_ctrl_jtag_state_post_trans 21.640s 1257.568us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 12.580s 986.466us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 12.580s 986.466us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 16.780s 1291.853us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.090s 507.806us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.090s 507.806us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 6 10 60.00
lc_ctrl_stress_all_with_rand_reset 56.530s 12473.503us 6 10 60.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 6 test runs
lc_ctrl_jtag_errors 16667628167282489267612265969441470897574908164803249679765728174347085833970 3068
UVM_INFO @ 7739761255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 18167112388550834240996026841566189932033418474299762279477007020275682437965 1027
UVM_INFO @ 64076949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 44060546442615477508967100318202310556820068898620784683232768435150589875697 2442
UVM_INFO @ 222780408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 103396033001680167246554991537276181159784931709554324531383916094503222606740 1842
UVM_INFO @ 741527571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 108126328722333701760773343051617821621922861395759924964915405463579837006145 3423
UVM_INFO @ 3324773228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 7864496113367246697327813327956258231143157116373043351728431355869980232634 1792
UVM_INFO @ 676248321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 25123033967038052076336557916868771170368687260780659181652863477293350061479 1214
UVM_INFO @ 1093671121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 36018880129998561045116444087020985038643195595649106578236638393580261268299 683
UVM_INFO @ 7072966216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 24295288548396809863327284956178364993401028983878760804922846899408645981889 1264
UVM_INFO @ 12473503436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 6005042369317766120569740728040903812288277264413600269461264130983047526088 5886
UVM_INFO @ 15241071811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---