Simulation Results: otp_ctrl

 
27/06/2026 02:42:03 DVSim: v1.49.0 sha: 1134d70 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.38 %
  • code
  • 86.09 %
  • assert
  • 95.52 %
  • func
  • 92.52 %
  • line
  • 90.35 %
  • branch
  • 86.89 %
  • cond
  • 93.97 %
  • toggle
  • 95.72 %
  • FSM
  • 63.54 %
Validation stages
V1
96.15%
V2
96.02%
V2S
95.61%
V3
21.78%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.650s 106.650us 1 1 100.00
smoke 10 10 100.00
otp_ctrl_smoke 12.590s 1858.636us 10 10 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.420s 106.332us 1 1 100.00
csr_rw 5 5 100.00
otp_ctrl_csr_rw 1.790s 606.034us 5 5 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 8.180s 658.728us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.870s 118.019us 1 1 100.00
csr_mem_rw_with_rand_reset 4 5 80.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.680s 222.701us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otp_ctrl_csr_rw 1.790s 606.034us 5 5 100.00
otp_ctrl_csr_aliasing 3.870s 118.019us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.490s 40.236us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.300s 96.520us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 15.160s 365.872us 1 1 100.00
init_fail 300 300 100.00
otp_ctrl_init_fail 7.860s 2912.551us 300 300 100.00
partition_check 37 60 61.67
otp_ctrl_background_chks 22.050s 15608.245us 10 10 100.00
otp_ctrl_check_fail 33.020s 4270.099us 27 50 54.00
regwen_during_otp_init 30 30 100.00
otp_ctrl_regwen 15.240s 5743.894us 30 30 100.00
partition_lock 30 30 100.00
otp_ctrl_dai_lock 59.070s 24108.539us 30 30 100.00
interface_key_check 10 10 100.00
otp_ctrl_parallel_key_req 24.100s 2854.544us 10 10 100.00
lc_interactions 210 210 100.00
otp_ctrl_parallel_lc_req 23.640s 11205.805us 10 10 100.00
otp_ctrl_parallel_lc_esc 41.220s 20099.047us 200 200 100.00
otp_dai_errors 24 25 96.00
otp_ctrl_dai_errs 42.260s 30097.081us 24 25 96.00
otp_macro_errors 4 10 40.00
otp_ctrl_macro_errs 23.720s 12177.749us 4 10 40.00
test_access 10 10 100.00
otp_ctrl_test_access 57.510s 10289.241us 10 10 100.00
stress_all 10 10 100.00
otp_ctrl_stress_all 139.320s 22239.891us 10 10 100.00
intr_test 10 10 100.00
otp_ctrl_intr_test 1.870s 41.606us 10 10 100.00
alert_test 10 10 100.00
otp_ctrl_alert_test 2.420s 1044.375us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otp_ctrl_tl_errors 6.110s 586.898us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otp_ctrl_tl_errors 6.110s 586.898us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.420s 106.332us 1 1 100.00
otp_ctrl_csr_rw 1.790s 606.034us 5 5 100.00
otp_ctrl_csr_aliasing 3.870s 118.019us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.730s 165.479us 5 5 100.00
tl_d_partial_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.420s 106.332us 1 1 100.00
otp_ctrl_csr_rw 1.790s 606.034us 5 5 100.00
otp_ctrl_csr_aliasing 3.870s 118.019us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.730s 165.479us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
tl_intg_err 30 30 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
otp_ctrl_tl_intg_err 24.180s 20297.620us 25 25 100.00
prim_count_check 5 5 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
prim_fsm_check 5 5 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
otp_ctrl_tl_intg_err 24.180s 20297.620us 25 25 100.00
sec_cm_secret_mem_scramble 10 10 100.00
otp_ctrl_smoke 12.590s 1858.636us 10 10 100.00
sec_cm_part_mem_digest 10 10 100.00
otp_ctrl_smoke 12.590s 1858.636us 10 10 100.00
sec_cm_dai_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
sec_cm_kdi_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
sec_cm_lci_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
sec_cm_part_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
sec_cm_scrmbl_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
sec_cm_timer_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
sec_cm_dai_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
sec_cm_kdi_seed_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
sec_cm_kdi_entropy_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
sec_cm_lci_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
sec_cm_part_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
sec_cm_scrmbl_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
sec_cm_timer_integ_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
sec_cm_timer_cnsty_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
sec_cm_timer_lfsr_redun 5 5 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
sec_cm_dai_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 41.220s 20099.047us 200 200 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
sec_cm_lci_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 41.220s 20099.047us 200 200 100.00
sec_cm_kdi_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 41.220s 20099.047us 200 200 100.00
sec_cm_part_fsm_local_esc 204 210 97.14
otp_ctrl_parallel_lc_esc 41.220s 20099.047us 200 200 100.00
otp_ctrl_macro_errs 23.720s 12177.749us 4 10 40.00
sec_cm_scrmbl_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 41.220s 20099.047us 200 200 100.00
sec_cm_timer_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 41.220s 20099.047us 200 200 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
sec_cm_dai_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 41.220s 20099.047us 200 200 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
sec_cm_lci_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 41.220s 20099.047us 200 200 100.00
sec_cm_kdi_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 41.220s 20099.047us 200 200 100.00
sec_cm_part_fsm_global_esc 204 210 97.14
otp_ctrl_parallel_lc_esc 41.220s 20099.047us 200 200 100.00
otp_ctrl_macro_errs 23.720s 12177.749us 4 10 40.00
sec_cm_scrmbl_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 41.220s 20099.047us 200 200 100.00
sec_cm_timer_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 41.220s 20099.047us 200 200 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
sec_cm_part_data_reg_integrity 300 300 100.00
otp_ctrl_init_fail 7.860s 2912.551us 300 300 100.00
sec_cm_part_data_reg_bkgn_chk 27 50 54.00
otp_ctrl_check_fail 33.020s 4270.099us 27 50 54.00
sec_cm_part_mem_regren 30 30 100.00
otp_ctrl_dai_lock 59.070s 24108.539us 30 30 100.00
sec_cm_part_mem_sw_unreadable 30 30 100.00
otp_ctrl_dai_lock 59.070s 24108.539us 30 30 100.00
sec_cm_part_mem_sw_unwritable 30 30 100.00
otp_ctrl_dai_lock 59.070s 24108.539us 30 30 100.00
sec_cm_lc_part_mem_sw_noaccess 30 30 100.00
otp_ctrl_dai_lock 59.070s 24108.539us 30 30 100.00
sec_cm_access_ctrl_mubi 30 30 100.00
otp_ctrl_dai_lock 59.070s 24108.539us 30 30 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
otp_ctrl_smoke 12.590s 1858.636us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 30 30 100.00
otp_ctrl_dai_lock 59.070s 24108.539us 30 30 100.00
sec_cm_test_bus_lc_gated 10 10 100.00
otp_ctrl_smoke 12.590s 1858.636us 10 10 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 135.170s 20096.745us 5 5 100.00
sec_cm_direct_access_config_regwen 30 30 100.00
otp_ctrl_regwen 15.240s 5743.894us 30 30 100.00
sec_cm_check_trigger_config_regwen 10 10 100.00
otp_ctrl_smoke 12.590s 1858.636us 10 10 100.00
sec_cm_check_config_regwen 10 10 100.00
otp_ctrl_smoke 12.590s 1858.636us 10 10 100.00
sec_cm_macro_mem_integrity 4 10 40.00
otp_ctrl_macro_errs 23.720s 12177.749us 4 10 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 16.130s 8078.179us 1 1 100.00
stress_all_with_rand_reset 21 100 21.00
otp_ctrl_stress_all_with_rand_reset 160.980s 19772.338us 21 100 21.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 41 test runs
otp_ctrl_check_fail 58832280220824046289911658825524840198185381300877889250594890495708798928916 6886
UVM_INFO @ 4760981799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 27750485697119074546540730029364818164565059442820979398919691784365736552074 7905
UVM_INFO @ 12177749200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 20465815404767914718123999237438739611365518610527855361039429344171444236452 309
UVM_INFO @ 70846183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 60545890007171018384831850665630986247060272451094452267934268614079078491005 3888
UVM_INFO @ 1603522606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 100054696260973897551255977862349855418942452578639491190945033928460989763006 10149
UVM_INFO @ 392751831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 58834108832940365517483736336385520626855938869994170626723535079827300031731 716
UVM_INFO @ 127454062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 108445171265938535118302902849691225895005695955879400459376822375142244528446 769
UVM_INFO @ 206877064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 81986850379753307873058389335496388260978107550618976928368004428007388396567 5858
UVM_INFO @ 463306686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 38052124509086703746537620399224653656357435943467653459943515168616525388886 8424
UVM_INFO @ 11146322611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 54522237054569719094298043958729159484458379772989946431043648924872016558908 663
UVM_INFO @ 130915330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 88778699783360664229913067541034883908485067449233749999763909621939838650192 475
UVM_INFO @ 136624123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 44141919037952865439313142159874955990325012077173323642951896080912533711400 2789
UVM_INFO @ 415893485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 25216746335088178063916741837054201697291350570129064058702369153470810003829 1960
UVM_INFO @ 239039663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 90266781329399171081883526343915290409616873686578504120669704535270310795791 1172
UVM_INFO @ 1730628358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 67363617255646562078968289086918962065098328218080078437019176984161826918156 21526
UVM_INFO @ 11534496359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 87726649112563569856472572378960853090704530383861240265221555872007460380742 1127
UVM_INFO @ 223877082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 29119637281092739958162338947150413201977338079926714329766119166660541011370 10578
UVM_INFO @ 2452733361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 87466683473427078738776403012989414905660311151193525991227501882817382827729 10746
UVM_INFO @ 560634285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 76310550612694463763681268722780000841239411030900629611683225623850946712690 2394
UVM_INFO @ 1020527022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 57066496780155824884866671239654306389786553994371231124083051853342279456272 3471
UVM_INFO @ 1409807407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 60008067551802515442916537586309184378600180091999092181546615778483838561197 759
UVM_INFO @ 110223016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 105033295964539276696386409378296651871489390314351418313701528334718031910141 3892
UVM_INFO @ 2138054981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 60792694766373147718255957466750948061986769185885377080428907735570567851013 627
UVM_INFO @ 478771919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 113446661765524811382439662241686952471376027446272984813237071498223454098056 2482
UVM_INFO @ 456304615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 26963799484826731729046028925026437214669218460379444669188920006029282692900 2627
UVM_INFO @ 152471311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 35387607468893421974308441339222935351326595579914098021699333638348286045783 2379
UVM_INFO @ 64663191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 24297143864315918965860760445453233884639704573133158354658823231257251672629 243
UVM_INFO @ 560866317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 42386855364230757647323184396025524586841884280692092207629744595129439652828 6982
UVM_INFO @ 806467510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 104117918354897152033643934869290764993034441504913166561201587536860032494486 14270
UVM_INFO @ 1347885061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 38174547064823896371563582990805234158065758439358606884626434744561683111914 1002
UVM_INFO @ 531206539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 52820309123825495363556141000193433505096195090131939420018623800828179681571 244
UVM_INFO @ 4317669410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 23365967181037934540629541852807117139755751450273310763062089042725855716104 5872
UVM_INFO @ 4270099333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 39311414501330019245404329757849903080101983979430323069401994569212471675119 1433
UVM_INFO @ 229997277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 12330895898682244319381606192648205089930872899246152607276552090779438698938 2451
UVM_INFO @ 204410801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 17485942332891874271689816809234383637964046694519494127625780531357310688072 1504
UVM_INFO @ 1986718367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 77957728901235730546465103043847602674107334005563133737587083256825075214430 194
UVM_INFO @ 815918795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 3072761680034762128447496653366149074313908776112656423175559509183070075672 16375
UVM_INFO @ 49809670256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 95685580116241270083760844046514950643279258126881044457413920264995941621149 917
UVM_INFO @ 19634615635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 107157365505657520854956354126484956001501813112802983332807679020306247588949 1045
UVM_INFO @ 3150278642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 112041519316858540813587229448145932237016340012830553534834683144560624120038 4134
UVM_INFO @ 1322090095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 1346124860650416796547522455239474959107616206305946621410650998635872820111 11531
UVM_INFO @ 18030845309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 22 test runs
otp_ctrl_stress_all_with_rand_reset 110991396047008107917637568293817433419376189766908518906302661767513833128747 16209
UVM_INFO @ 7498043095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 107444805312725237012030172630586542862419866075299608324213125141325304838698 454
UVM_INFO @ 73614849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 61602860390468073727059738218136358201228233221721363865339928214231058975596 22690
UVM_INFO @ 7063359749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4222407288846717858431051949997936184288313729739106258590875567201141700784 92
UVM_INFO @ 103450845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 63801348463152513713241197004433614337478156991671134847320130132981990021046 62770
UVM_INFO @ 4219295248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 10734474280890854858385285274989600491880845841801128884290356811533592674549 92
UVM_INFO @ 27941589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 63419018720014787230397854660696602483809156137920987842391723954195968548665 92
UVM_INFO @ 40588123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 22822109911800772472026100424248124832933152914558016199127466589524148343988 92
UVM_INFO @ 39870501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 14480531887330642815665708377273135710587014334148968480567363137549666520704 28283
UVM_INFO @ 3404304865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 84876127775139083917740331343084850475477100629161446571314161997373102871875 230
UVM_INFO @ 228304926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 66827729861467798724036839867373547234444715477338986782207736380433468277720 92
UVM_INFO @ 63742450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 92752965134824890615055152679472737565120426969639967894566599784108231182905 92
UVM_INFO @ 108301122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 113525076580639186173888095054379302358568360275913386342139165263737304748903 10620
UVM_INFO @ 16749335042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 53449405854619317183497482118716411935090561599100144023929997980739339798220 28529
UVM_INFO @ 3518737417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 53826416828763893998573238740407967286114622833974758085698061616942523604276 28985
UVM_INFO @ 2594975833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 32641257613156297029863701134763355687555688519868150664204689563339245091941 92
UVM_INFO @ 102888692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 7626934832015521522275977613607781827599458130293935797312765745307832267538 18246
UVM_INFO @ 13106293425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 65630832339619116154395152164963322152864076793486122422524062593625218041359 5236
UVM_INFO @ 5822081567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 103471125553879819989710543990747922382352474588409579277276472432229608477447 23088
UVM_INFO @ 841977169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 98101931042238078348943481266271787356921989719246197055432915015625899541395 13479
UVM_INFO @ 2919109809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 46145581861393704405208810555718401584534875353912780188750194223886444849587 137
UVM_INFO @ 270546545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 105535867308859760139117382728464235187110840551952256937797816823979336967532 835
UVM_INFO @ 11310024500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 19 test runs
otp_ctrl_stress_all_with_rand_reset 3801711413771005267951095837023415784087358875915237221675610477127915997388 11740
UVM_INFO @ 5686103101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 64142380364741775936618386947981825587134119580614065048028854913339758199007 4045
UVM_INFO @ 16523525609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4286971430058387955899538286587358952165266515124348244581451290785508804845 5545
UVM_INFO @ 13858732308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76666745784720029202575969493383293162479500893987344256047708054434538312317 12204
UVM_INFO @ 7627106756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42693889323844000790180498350338308861507689082936377843065207637987622036447 4301
UVM_INFO @ 4669695464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 94843008842217770590384202215862484597514856906003870556774636677261827965751 835
UVM_INFO @ 205834388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 17576930538040686577657662525763057375310276319683174114983597706267174825999 9596
UVM_INFO @ 9374643964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 58713255427269659301533022507563693993422595206387096829338055632828818584358 4670
UVM_INFO @ 2778036898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 29602386814560727774611332139430826391863253806904676444263751828703435425848 9082
UVM_INFO @ 2416591852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 41798904859273834518539585953938152827284366536392915808905888043037435282731 1570
UVM_INFO @ 2589904756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 48547774234085056808994637409644023626649583666379222778333478482608019264908 17522
UVM_INFO @ 7117629588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 13978172584072734294479648021573018956293699193890160868968869729626587824898 163
UVM_INFO @ 32185462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 54166702608767495113706280091302921880676869793246963702609025201679248676642 690
UVM_INFO @ 201544653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42519298395130856683822001470845668565766333373743230674003995269187772710743 1567
UVM_INFO @ 1025720891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 30153393360749013457949267831643059732926172125080770018063415512143493281307 474
UVM_INFO @ 2483965995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 109727557488668443819669148931064119167870995504807654741844222335068337915933 5257
UVM_INFO @ 716165995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 87561604634910823201739948565703901874005815119267265705167934127855072900080 5584
UVM_INFO @ 25505664694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 84148240289459979355458241300399034033557381517625190654457420710805189434499 24981
UVM_INFO @ 2912600636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 48767204750423115526616365912848457971430007058511792313089808263704772614181 15029
UVM_INFO @ 1626719069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 15 test runs
otp_ctrl_csr_mem_rw_with_rand_reset 60248197926265914971336056244123829252842172798864733960668337571502312900490 92
UVM_INFO @ 430734777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 21098195356720033796451764888247737327898648509035260909359623721269703056275 1472
UVM_INFO @ 4806553722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 10444289680982762082878112623036122306020883455830854325100954148485371921634 26328
UVM_INFO @ 10517522009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 66263143310136443531326736550224047946935583733489715426455250791126454379918 4192
UVM_INFO @ 3194897722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 6917959087927300371286987226574466955008189472649814871421769760081212223939 10048
UVM_INFO @ 501252645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 72232588502930574123351608357990334341335681413734190490342502944588205087839 92
UVM_INFO @ 53956537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 78725028290091181731278725346929294221490446559528179957735554469564558207512 9111
UVM_INFO @ 15438914764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 100227322617883027023770351362119644854615290372772927849957751771369004240837 2926
UVM_INFO @ 790198456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80899595054594284627692102650560276652893343131311374408106435456485016396291 92
UVM_INFO @ 31529944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 75162111422396994603356537959101049894524486335589600995241243218992736618876 292
UVM_INFO @ 66222314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 87248930301629581568111288496053752447556809291502154868155561718247445468523 184
UVM_INFO @ 3729420553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 83921670370156288655626343813206240034241507451964242178824032267255083716536 92
UVM_INFO @ 27237234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 113017843262854087565822650355165604933746965055900029346506628926644153643586 8700
UVM_INFO @ 795248017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 84650790859769325360663143740743247678814653508641357410598670880006561179188 373
UVM_INFO @ 302097373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 24606956616022109056722010707516237573054960306249151117334953259392252869209 5526
UVM_INFO @ 4517979514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
otp_ctrl_stress_all_with_rand_reset 15823860817047361243523058771472851290912384590195972922052474780510220180437 14484
UVM_INFO @ 29779824233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 39042582124506194642680152813731526549735511522934178966322048096965571849534 28676
UVM_INFO @ 65958453242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 104020755622464234171859092657712618843046953799963037580856951139064741077774 9546
UVM_INFO @ 21767357077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 55926923585727597736403763655495561542532355050094971669584740103097874416840 8326
UVM_INFO @ 3330763338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 91073824589558613916379056419949953804250993237235149281613921278741067690114 17896
UVM_INFO @ 29508317190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 2 test runs
otp_ctrl_stress_all_with_rand_reset 16841723076962347807271506984118488469563172258677915912380693199999361390317 7857
UVM_INFO @ 30281831130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 87891225168135729707499204256600863358529640672132079057985329475451446189991 26967
UVM_INFO @ 61617685479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(cio_test_en_o == *)' 2 test runs
otp_ctrl_stress_all_with_rand_reset 73301910773093988289635428752974620124084305293546451077017812348259156564786 4806
UVM_ERROR @ 6106028518 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 6106028518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 40808830367993984880390093993991231139372236646471347702462040789826839483507 7230
UVM_ERROR @ 20205298300 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 20205298300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_common_vseq] wait timeout occurred! 2 test runs
otp_ctrl_stress_all_with_rand_reset 36230112913305432558584514486941153607397297865796284063895200011606003649943 464
UVM_INFO @ 10111052471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 39843424144331656382690946075736551683599962750120666828504484328783306402732 1702
UVM_INFO @ 10575659994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *bc rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 42619680941912953743411693869484996274530271015969555907345506100676417778759 3934
UVM_INFO @ 9043738050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 45539267746839077745012733809289725884031360886243611717000419058179580927165 2278
UVM_INFO @ 32120180157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---