Simulation Results: pwrmgr

 
27/06/2026 02:42:03 DVSim: v1.49.0 sha: 1134d70 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.50 %
  • code
  • 97.54 %
  • assert
  • 98.96 %
  • func
  • 99.01 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 96.61 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
94.16%
V2S
100.00%
V3
65.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
pwrmgr_smoke 0.800s 31.285us 10 10 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.740s 77.594us 1 1 100.00
csr_rw 5 5 100.00
pwrmgr_csr_rw 0.850s 28.794us 5 5 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 3.220s 1362.511us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.090s 152.640us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.320s 74.764us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
pwrmgr_csr_rw 0.850s 28.794us 5 5 100.00
pwrmgr_csr_aliasing 1.090s 152.640us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 10 10 100.00
pwrmgr_wakeup 1.150s 285.373us 10 10 100.00
control_clks 10 10 100.00
pwrmgr_wakeup 1.150s 285.373us 10 10 100.00
aborted_low_power 20 20 100.00
pwrmgr_aborted_low_power 1.140s 43.689us 10 10 100.00
pwrmgr_lowpower_invalid 0.840s 45.823us 10 10 100.00
reset 17 20 85.00
pwrmgr_reset 1.020s 277.504us 10 10 100.00
pwrmgr_reset_invalid 1.070s 99.380us 7 10 70.00
main_power_glitch_reset 10 10 100.00
pwrmgr_reset 1.020s 277.504us 10 10 100.00
reset_wakeup_race 10 10 100.00
pwrmgr_wakeup_reset 1.270s 234.322us 10 10 100.00
lowpower_wakeup_race 10 10 100.00
pwrmgr_lowpower_wakeup_race 1.170s 133.051us 10 10 100.00
disable_rom_integrity_check 8 10 80.00
pwrmgr_disable_rom_integrity_check 2.050s 1000.000us 8 10 80.00
stress_all 7 10 70.00
pwrmgr_stress_all 23.320s 10704.166us 7 10 70.00
intr_test 10 10 100.00
pwrmgr_intr_test 0.820s 46.110us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
pwrmgr_tl_errors 2.110s 175.111us 25 25 100.00
tl_d_illegal_access 25 25 100.00
pwrmgr_tl_errors 2.110s 175.111us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
pwrmgr_csr_hw_reset 0.740s 77.594us 1 1 100.00
pwrmgr_csr_rw 0.850s 28.794us 5 5 100.00
pwrmgr_csr_aliasing 1.090s 152.640us 1 1 100.00
pwrmgr_same_csr_outstanding 1.190s 148.969us 5 5 100.00
tl_d_partial_access 12 12 100.00
pwrmgr_csr_hw_reset 0.740s 77.594us 1 1 100.00
pwrmgr_csr_rw 0.850s 28.794us 5 5 100.00
pwrmgr_csr_aliasing 1.090s 152.640us 1 1 100.00
pwrmgr_same_csr_outstanding 1.190s 148.969us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
pwrmgr_tl_intg_err 2.040s 209.092us 25 25 100.00
pwrmgr_sec_cm 1.560s 652.566us 5 5 100.00
prim_count_check 5 5 100.00
pwrmgr_sec_cm 1.560s 652.566us 5 5 100.00
prim_fsm_check 5 5 100.00
pwrmgr_sec_cm 1.560s 652.566us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
pwrmgr_tl_intg_err 2.040s 209.092us 25 25 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.620s 821.759us 10 10 100.00
sec_cm_rom_ctrl_intersig_mubi 20 20 100.00
pwrmgr_wakeup_reset 1.270s 234.322us 10 10 100.00
pwrmgr_repeat_wakeup_reset 2.640s 956.765us 10 10 100.00
sec_cm_rstmgr_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.060s 109.662us 10 10 100.00
sec_cm_esc_rx_clk_bkgn_chk 10 10 100.00
pwrmgr_esc_clk_rst_malfunc 0.850s 30.102us 10 10 100.00
sec_cm_esc_rx_clk_local_esc 5 5 100.00
pwrmgr_sec_cm 1.560s 652.566us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
pwrmgr_sec_cm 1.560s 652.566us 5 5 100.00
sec_cm_fsm_terminal 5 5 100.00
pwrmgr_sec_cm 1.560s 652.566us 5 5 100.00
sec_cm_ctrl_flow_global_esc 10 10 100.00
pwrmgr_global_esc 0.770s 28.828us 10 10 100.00
sec_cm_main_pd_rst_local_esc 10 10 100.00
pwrmgr_glitch 0.840s 76.552us 10 10 100.00
sec_cm_ctrl_config_regwen 10 10 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.220s 206.533us 10 10 100.00
sec_cm_wakeup_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.850s 28.794us 5 5 100.00
sec_cm_reset_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.850s 28.794us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 3 10 30.00
pwrmgr_escalation_timeout 0.950s 98.125us 3 10 30.00
stress_all_with_rand_reset 10 10 100.00
pwrmgr_stress_all_with_rand_reset 10.120s 7870.348us 10 10 100.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)' 7 test runs
pwrmgr_escalation_timeout 7661939633013902277205401412210820176198990581437717163849362601481932124229 79
UVM_ERROR @ 98124666 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 98124666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 48107934170655077770930927340650163780600128403702985606905369528788143292267 79
UVM_ERROR @ 1090356167 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 1090356167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 1435073338675836630891200241830927919021933551538059549272744847671122298850 79
UVM_ERROR @ 262502647 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 262502647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 45483794429076370343241404278339555606430667923999233567346645215260680100184 79
UVM_ERROR @ 732202874 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 732202874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 11353709330022824356213132349808572317702790654542704856284778854082472254564 79
UVM_ERROR @ 356535258 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 356535258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 52008262478950918540246826017000707611623778737527204964429412976670237708859 79
UVM_ERROR @ 97510741 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 97510741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 729092597962223551145607559808016318308715066280202396877863261836599966816 79
UVM_ERROR @ 264242896 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 264242896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 3 test runs
pwrmgr_stress_all 52640191040038973542413216373423106066697002644005232061928695426897715787527 389
UVM_INFO @ 10378268297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 94206999464060382872686935123680713541031498395903464457511157674344196585512 518
UVM_INFO @ 10704166317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 72773072351593321498968202808376754215312262927641136794636278840479319981627 595
UVM_INFO @ 11030425496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
pwrmgr_disable_rom_integrity_check 67090931459408499080093944198592488246484958634550272019600401085850154525216 92
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 47064391878841398229967607361384032168110560159848806514072179516778320208907 114
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitStrap 1 test run
pwrmgr_reset_invalid 101672411212350023155335154757990392365758778805693023903607420681159807576928 269
UVM_INFO @ 102535298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitNvmShutDown 1 test run
pwrmgr_reset_invalid 57666264891118751812376164410191349563245194251166424218429820080188147119988 110
UVM_INFO @ 32982672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitOtpInit 1 test run
pwrmgr_reset_invalid 40273941994267219216293639461193215124985361534812525269792390345150184212999 189
UVM_INFO @ 70240342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---