Simulation Results: rom_ctrl/32kb

 
27/06/2026 02:42:03 DVSim: v1.49.0 sha: 1134d70 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.53 %
  • code
  • 98.77 %
  • assert
  • 97.53 %
  • func
  • 99.28 %
  • line
  • 99.46 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 95.57 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
96.61%
V3
95.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 5.270s 222.694us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.930s 267.510us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 6.090s 164.665us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.580s 385.351us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.740s 576.313us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.060s 182.569us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 6.090s 164.665us 5 5 100.00
rom_ctrl_csr_aliasing 3.740s 576.313us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.170s 371.601us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.200s 169.575us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 3.480s 87.762us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 25.880s 1551.718us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 8.220s 307.468us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 7.800s 1028.691us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 13.770s 202.432us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 13.770s 202.432us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 7.930s 267.510us 1 1 100.00
rom_ctrl_csr_rw 6.090s 164.665us 5 5 100.00
rom_ctrl_csr_aliasing 3.740s 576.313us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.590s 599.349us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 7.930s 267.510us 1 1 100.00
rom_ctrl_csr_rw 6.090s 164.665us 5 5 100.00
rom_ctrl_csr_aliasing 3.740s 576.313us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.590s 599.349us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 110.110s 41170.889us 18 20 90.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 25.310s 1670.205us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 279.010s 2797.738us 5 5 100.00
rom_ctrl_tl_intg_err 69.500s 554.771us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 279.010s 2797.738us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 279.010s 2797.738us 5 5 100.00
sec_cm_checker_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 110.110s 41170.889us 18 20 90.00
sec_cm_checker_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 110.110s 41170.889us 18 20 90.00
sec_cm_checker_fsm_local_esc 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 110.110s 41170.889us 18 20 90.00
sec_cm_compare_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 110.110s 41170.889us 18 20 90.00
sec_cm_compare_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 110.110s 41170.889us 18 20 90.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 279.010s 2797.738us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 279.010s 2797.738us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 5.270s 222.694us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 5.270s 222.694us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 5.270s 222.694us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 69.500s 554.771us 25 25 100.00
sec_cm_bus_local_esc 20 22 90.91
rom_ctrl_corrupt_sig_fatal_chk 110.110s 41170.889us 18 20 90.00
rom_ctrl_kmac_err_chk 8.220s 307.468us 2 2 100.00
sec_cm_mux_mubi 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 110.110s 41170.889us 18 20 90.00
sec_cm_mux_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 110.110s 41170.889us 18 20 90.00
sec_cm_ctrl_redun 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 110.110s 41170.889us 18 20 90.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 25.310s 1670.205us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 279.010s 2797.738us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 19 20 95.00
rom_ctrl_stress_all_with_rand_reset 339.950s 4304.731us 19 20 95.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 31337582972542903407173094588234442789668974962106942226321602258976968283355 79
UVM_INFO @ 87762350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 79788044297993675910668618293262694187853336187825679897132552463331953352053 79
UVM_INFO @ 89523731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 2 test runs
rom_ctrl_corrupt_sig_fatal_chk 83752358867670719593770199975022098843645566408645065672466706440463020265849 91
UVM_INFO @ 711124313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 46793316848303036324705006041688387934281447573370171217654018254260824124527 80
UVM_INFO @ 323544012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:235) [scoreboard] Check failed item.d_data[i**+:*] == exp_data[i**+:*] (* [*] vs * [*]) TLUL ROM read data incorrect 1 test run
rom_ctrl_stress_all_with_rand_reset 86591619118794387363830616099236566213372073849913724674263631853446389309599 98
UVM_INFO @ 939362315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---