Simulation Results: rom_ctrl/64kb

 
27/06/2026 02:42:03 DVSim: v1.49.0 sha: 1134d70 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.58 %
  • code
  • 98.77 %
  • assert
  • 97.68 %
  • func
  • 99.28 %
  • line
  • 99.46 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 95.57 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 13.980s 310.524us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.430s 211.468us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 13.890s 2027.150us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 11.740s 292.754us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.210s 700.110us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 10.260s 430.783us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 13.890s 2027.150us 5 5 100.00
rom_ctrl_csr_aliasing 7.210s 700.110us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 9.860s 287.689us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 11.450s 287.518us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 9.150s 257.716us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 46.040s 5615.581us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 19.480s 387.367us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 12.380s 5511.985us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 15.500s 354.270us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 15.500s 354.270us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 10.430s 211.468us 1 1 100.00
rom_ctrl_csr_rw 13.890s 2027.150us 5 5 100.00
rom_ctrl_csr_aliasing 7.210s 700.110us 1 1 100.00
rom_ctrl_same_csr_outstanding 12.450s 215.698us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 10.430s 211.468us 1 1 100.00
rom_ctrl_csr_rw 13.890s 2027.150us 5 5 100.00
rom_ctrl_csr_aliasing 7.210s 700.110us 1 1 100.00
rom_ctrl_same_csr_outstanding 12.450s 215.698us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 224.840s 25111.684us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 77.800s 66068.366us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 586.040s 4623.709us 5 5 100.00
rom_ctrl_tl_intg_err 156.490s 331.105us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 586.040s 4623.709us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 586.040s 4623.709us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 224.840s 25111.684us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 224.840s 25111.684us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 224.840s 25111.684us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 224.840s 25111.684us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 224.840s 25111.684us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 586.040s 4623.709us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 586.040s 4623.709us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 13.980s 310.524us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 13.980s 310.524us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 13.980s 310.524us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 156.490s 331.105us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 224.840s 25111.684us 20 20 100.00
rom_ctrl_kmac_err_chk 19.480s 387.367us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 224.840s 25111.684us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 224.840s 25111.684us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 224.840s 25111.684us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 77.800s 66068.366us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 586.040s 4623.709us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 268.280s 4324.506us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 56798297602740319215928438508451810524478654486843122195323784089735365147233 79
UVM_INFO @ 248650244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 1975759369721271829306493963571939424658408408494072644639976544660997332398 79
UVM_INFO @ 257716178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---