| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 5 | 5 | 100.00 | |||
| rstmgr_smoke | 2.070s | 298.703us | 5 | 5 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rstmgr_csr_hw_reset | 1.210s | 103.497us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| rstmgr_csr_rw | 1.160s | 67.540us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rstmgr_csr_bit_bash | 10.740s | 2851.930us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rstmgr_csr_aliasing | 2.080s | 219.534us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| rstmgr_csr_mem_rw_with_rand_reset | 1.910s | 213.319us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| rstmgr_csr_rw | 1.160s | 67.540us | 5 | 5 | 100.00 | |
| rstmgr_csr_aliasing | 2.080s | 219.534us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_stretcher | 5 | 5 | 100.00 | |||
| rstmgr_por_stretcher | 1.430s | 225.322us | 5 | 5 | 100.00 | |
| sw_rst | 5 | 5 | 100.00 | |||
| rstmgr_sw_rst | 3.190s | 517.358us | 5 | 5 | 100.00 | |
| sw_rst_reset_race | 5 | 5 | 100.00 | |||
| rstmgr_sw_rst_reset_race | 1.780s | 299.484us | 5 | 5 | 100.00 | |
| reset_info | 5 | 5 | 100.00 | |||
| rstmgr_reset | 8.580s | 2045.294us | 5 | 5 | 100.00 | |
| cpu_info | 5 | 5 | 100.00 | |||
| rstmgr_reset | 8.580s | 2045.294us | 5 | 5 | 100.00 | |
| alert_info | 5 | 5 | 100.00 | |||
| rstmgr_reset | 8.580s | 2045.294us | 5 | 5 | 100.00 | |
| reset_info_capture | 5 | 5 | 100.00 | |||
| rstmgr_reset | 8.580s | 2045.294us | 5 | 5 | 100.00 | |
| stress_all | 5 | 5 | 100.00 | |||
| rstmgr_stress_all | 31.750s | 11840.491us | 5 | 5 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| rstmgr_alert_test | 1.220s | 96.818us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| rstmgr_tl_errors | 4.920s | 614.195us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| rstmgr_tl_errors | 4.920s | 614.195us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| rstmgr_csr_hw_reset | 1.210s | 103.497us | 1 | 1 | 100.00 | |
| rstmgr_csr_rw | 1.160s | 67.540us | 5 | 5 | 100.00 | |
| rstmgr_csr_aliasing | 2.080s | 219.534us | 1 | 1 | 100.00 | |
| rstmgr_same_csr_outstanding | 1.990s | 240.874us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| rstmgr_csr_hw_reset | 1.210s | 103.497us | 1 | 1 | 100.00 | |
| rstmgr_csr_rw | 1.160s | 67.540us | 5 | 5 | 100.00 | |
| rstmgr_csr_aliasing | 2.080s | 219.534us | 1 | 1 | 100.00 | |
| rstmgr_same_csr_outstanding | 1.990s | 240.874us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| rstmgr_sec_cm | 30.590s | 17379.959us | 5 | 5 | 100.00 | |
| rstmgr_tl_intg_err | 3.760s | 955.830us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| rstmgr_sec_cm | 30.590s | 17379.959us | 5 | 5 | 100.00 | |
| prim_fsm_check | 5 | 5 | 100.00 | |||
| rstmgr_sec_cm | 30.590s | 17379.959us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| rstmgr_tl_intg_err | 3.760s | 955.830us | 25 | 25 | 100.00 | |
| sec_cm_scan_intersig_mubi | 5 | 5 | 100.00 | |||
| rstmgr_sec_cm_scan_intersig_mubi | 1.600s | 205.941us | 5 | 5 | 100.00 | |
| sec_cm_leaf_rst_bkgn_chk | 25 | 25 | 100.00 | |||
| rstmgr_leaf_rst_cnsty | 10.170s | 2801.796us | 25 | 25 | 100.00 | |
| sec_cm_leaf_rst_shadow | 5 | 5 | 100.00 | |||
| rstmgr_leaf_rst_shadow_attack | 1.750s | 302.525us | 5 | 5 | 100.00 | |
| sec_cm_leaf_fsm_sparse | 5 | 5 | 100.00 | |||
| rstmgr_sec_cm | 30.590s | 17379.959us | 5 | 5 | 100.00 | |
| sec_cm_sw_rst_config_regwen | 5 | 5 | 100.00 | |||
| rstmgr_csr_rw | 1.160s | 67.540us | 5 | 5 | 100.00 | |
| sec_cm_dump_ctrl_config_regwen | 5 | 5 | 100.00 | |||
| rstmgr_csr_rw | 1.160s | 67.540us | 5 | 5 | 100.00 | |