Simulation Results: rv_timer

 
27/06/2026 02:42:03 DVSim: v1.49.0 sha: 1134d70 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.40 %
  • code
  • 94.66 %
  • assert
  • 98.41 %
  • func
  • 99.12 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
85.04%
V2S
100.00%
V3
42.50%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 1.500s 1957.368us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.760s 13.467us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 0.900s 14.315us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.830s 607.235us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.760s 39.062us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.050s 33.007us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 0.900s 14.315us 5 5 100.00
rv_timer_csr_aliasing 0.760s 39.062us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 20 5.00
rv_timer_random_reset 3.080s 11668.408us 1 20 5.00
disabled 20 20 100.00
rv_timer_disabled 2.360s 2156.267us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 422.850s 734393.270us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 422.850s 734393.270us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 5.810s 3980.407us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 0.810s 12.576us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 0.890s 63.360us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 2.420s 47.753us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 2.420s 47.753us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 0.760s 13.467us 1 1 100.00
rv_timer_csr_rw 0.900s 14.315us 5 5 100.00
rv_timer_csr_aliasing 0.760s 39.062us 1 1 100.00
rv_timer_same_csr_outstanding 0.890s 14.982us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 0.760s 13.467us 1 1 100.00
rv_timer_csr_rw 0.900s 14.315us 5 5 100.00
rv_timer_csr_aliasing 0.760s 39.062us 1 1 100.00
rv_timer_same_csr_outstanding 0.890s 14.982us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 1.270s 178.679us 5 5 100.00
rv_timer_tl_intg_err 1.440s 194.954us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 1.440s 194.954us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 4 10 40.00
rv_timer_min 1.470s 1030.807us 4 10 40.00
max_value 0 10 0.00
rv_timer_max 1.410s 87.563us 0 10 0.00
stress_all_with_rand_reset 13 20 65.00
rv_timer_stress_all_with_rand_reset 45.390s 10565.046us 13 20 65.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 25 test runs
rv_timer_min 84340802696237588276763540412053167092185765196837035980123917157500436827438 77
UVM_INFO @ 373120269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 5781149695867374599912015444332126537855196933976504992861778532142659442279 76
UVM_INFO @ 110589567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 54459579871453081005905925873690165733135221044171506397680991861454222359923 76
UVM_INFO @ 1273309177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 52838348853851996095361319645152990225308753683209442843058975771839618367541 75
UVM_INFO @ 11668407906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 104248193082069889238129977361940910275652494544943847431055235687650251332887 76
UVM_INFO @ 11543407917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 110009186492323064934506621065583649103847587125013445252676425676598307959282 75
UVM_INFO @ 171918116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 55198462904589014167405680795519971071963036180841313947046142241927736278879 76
UVM_INFO @ 170367081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 62647891827308220528791096688389622506929553960945340650549191372467149614211 75
UVM_INFO @ 229533204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 38345989430155269405493370910408502662166014102151846585634429785397518928931 77
UVM_INFO @ 126012066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 110968284294102383333990494465785847861943084698604948531188260273388354950053 76
UVM_INFO @ 83539938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 105303440293201040632349184811769315578069951213365106650193024775804180804105 75
UVM_INFO @ 66465411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 87816488841955801904465870288982153156030634703429730170471945525713116125404 75
UVM_INFO @ 246186581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 106710039092986145704740261070388531032933045892261246489077430267921624109363 76
UVM_INFO @ 69856787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 55967229935157571262355862352051188352284815991223568722246328939809223256300 78
UVM_INFO @ 721516340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 112576328286816704306576993333669310517960891551216734910888480334321077097814 75
UVM_INFO @ 1030806813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 82549050487679906733359124669612030835025461532337857929710623200280301446750 75
UVM_INFO @ 333343015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 107084782809919430420621069091829690450608675058647160318603370925641437649592 75
UVM_INFO @ 3427151578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 30562608598113524362225367984564777778465142065818906019528554511374430562226 76
UVM_INFO @ 76285186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 21070246294548011293954917610170728458423187142038711884015671658924535745327 76
UVM_INFO @ 1242430166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 71194979138036572521282365224802937877545830848476735223096478835213466812122 75
UVM_INFO @ 153977878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 3536893667230148783633374876690069955962751150923142181997679642239328092717 76
UVM_INFO @ 880664937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 29601535515326374924556080476562533802393668658083505318699869630918396908895 75
UVM_INFO @ 272018986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 67250032385217492280421980034495158267756471854697867159744803023221800864049 75
UVM_INFO @ 261823773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 19551071914128985292292104858644610757992857984382175985037126002707795593394 75
UVM_INFO @ 1840618892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 70359688533842282971154040171448170363200130999937282829980297666075810877405 75
UVM_INFO @ 519019509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 9 test runs
rv_timer_max 115555644083284014297030076970742015685617119415225285375031483662834547134331 76
UVM_INFO @ 186653625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 84362738069240659310419103898624017055320409957018289826652774319442573707362 75
UVM_INFO @ 180257066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 7394470643743697050352099485403561011895251447722350995832100547818116293812 75
UVM_INFO @ 87404305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 74952542638910958423965313872895480517668785299877401264382155413380377702258 75
UVM_INFO @ 89133964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 38476536718187180671902415662159065157030535259753429074798011672769181304313 75
UVM_INFO @ 356228760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 98852934873989970577360625058498968176268240851232830532851831495165160199581 75
UVM_INFO @ 387449711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 71067978758812934911101306485862478482902587835595585544118259804892232536300 75
UVM_INFO @ 49326935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 75801043156221217546728909417146972754553382082401841464496060492366122567876 75
UVM_INFO @ 129699684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 92972007346143286440362202697482463034723982118512050610550187054479303797883 75
UVM_INFO @ 87563189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 4 test runs
rv_timer_stress_all_with_rand_reset 54492031016790938212175907677196805726901745203904378175905669542486766751999 284
UVM_INFO @ 5802370293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 83659902664645209209525721016010663173836453713705549723564738654663799522867 103
UVM_INFO @ 862883769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 85982301753913997122633510325366273684508244146252492364773818949699052866686 205
UVM_INFO @ 3492592270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 25933064518779576171349352166015519251991799144469414096907925706001896326976 101
UVM_INFO @ 12322522252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 3 test runs
rv_timer_stress_all_with_rand_reset 72018377661143730145965351169770288742099240988669405955296398092605471429240 79
UVM_INFO @ 9018438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 111650338396209524272197427974891752284308989746242863020412627122659574822881 362
UVM_INFO @ 14129293579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 13725094395184286003242071841532945111421737232939007994385121621798091478300 156
UVM_INFO @ 1742852855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 1 test run
rv_timer_max 42953317674433647237628020313553405855311765526087066023504301496049640407314 75
UVM_INFO @ 176875638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---