Simulation Results: spi_host

 
27/06/2026 02:42:03 DVSim: v1.49.0 sha: 1134d70 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.96 %
  • code
  • 91.32 %
  • assert
  • 96.79 %
  • func
  • 90.76 %
  • block
  • 97.01 %
  • line
  • 98.76 %
  • branch
  • 93.45 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.45%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 42.000s 1472.134us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 3.000s 19.022us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 3.000s 44.927us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 4.000s 74.831us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 4.000s 33.488us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 3.000s 38.131us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 3.000s 44.927us 5 5 100.00
spi_host_csr_aliasing 4.000s 33.488us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 14.663us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 19.814us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 40.698us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 4.000s 175.979us 10 10 100.00
spi_host_error_cmd 3.000s 198.297us 10 10 100.00
spi_host_event 86.000s 16391.429us 10 10 100.00
clock_rate 9 10 90.00
spi_host_speed 16.000s 10048.571us 9 10 90.00
speed 9 10 90.00
spi_host_speed 16.000s 10048.571us 9 10 90.00
chip_select_timing 9 10 90.00
spi_host_speed 16.000s 10048.571us 9 10 90.00
upper_range_clkdiv 5 5 100.00
spi_host_upper_range_clkdiv 738.000s 51787.673us 5 5 100.00
sw_reset 10 10 100.00
spi_host_sw_reset 67.000s 1768.673us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 27.675us 10 10 100.00
cpol_cpha 9 10 90.00
spi_host_speed 16.000s 10048.571us 9 10 90.00
full_cycle 9 10 90.00
spi_host_speed 16.000s 10048.571us 9 10 90.00
duplex 10 10 100.00
spi_host_smoke 42.000s 1472.134us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 42.000s 1472.134us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 49.000s 1369.562us 10 10 100.00
spien 10 10 100.00
spi_host_spien 229.000s 36355.408us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 1713.000s 137560.833us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 3.000s 298.478us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 4.000s 175.979us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 4.000s 18.344us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 45.531us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 4.000s 588.433us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 4.000s 588.433us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 3.000s 19.022us 1 1 100.00
spi_host_csr_rw 3.000s 44.927us 5 5 100.00
spi_host_csr_aliasing 4.000s 33.488us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 19.734us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 3.000s 19.022us 1 1 100.00
spi_host_csr_rw 3.000s 44.927us 5 5 100.00
spi_host_csr_aliasing 4.000s 33.488us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 19.734us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 163.239us 25 25 100.00
spi_host_sec_cm 2.000s 39.672us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 163.239us 25 25 100.00

Error Messages

   Test seed line log context
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* 1 test run
spi_host_speed 106371304466435803491141645145022481773743299870079659111328292052710824713622 238
UVM_INFO @ 10048570580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---