Simulation Results: sram_ctrl/main

 
27/06/2026 02:42:03 DVSim: v1.49.0 sha: 1134d70 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.85 %
  • code
  • 95.85 %
  • assert
  • 98.10 %
  • func
  • 96.60 %
  • block
  • 96.30 %
  • line
  • 97.05 %
  • branch
  • 94.50 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 7.000s 696.811us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 50.323us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 18.494us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 774.922us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 161.796us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.000s 1502.276us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 18.494us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 161.796us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 297.000s 111946.334us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 134.000s 11342.365us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 44.000s 27128.499us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 235.000s 11280.050us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 187.000s 17701.916us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 66.000s 40980.175us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 75.000s 24655.343us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 43.000s 131388.220us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 6.000s 2789.197us 8 8 100.00
sram_ctrl_partial_access_b2b 367.000s 25045.516us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 7.000s 1384.614us 0 8 0.00
sram_ctrl_throughput_w_partial_write 7.000s 1375.233us 0 8 0.00
sram_ctrl_throughput_w_readback 7.000s 2290.001us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 21.000s 2403.505us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 5.000s 467.124us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 506.000s 151793.714us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 22.828us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 5.000s 495.690us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 5.000s 495.690us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 50.323us 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.494us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 161.796us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 15.522us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 50.323us 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.494us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 161.796us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 15.522us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 44.000s 78448.110us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 5.000s 663.928us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 804.649us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 663.928us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 804.649us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 21.000s 2403.505us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 21.000s 2403.505us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 18.494us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 43.000s 131388.220us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 43.000s 131388.220us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 43.000s 131388.220us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 75.000s 24655.343us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 7.000s 703.766us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 44.000s 78448.110us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 7.000s 1285.946us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 7.000s 696.811us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 7.000s 696.811us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 43.000s 131388.220us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 663.928us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 75.000s 24655.343us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 663.928us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 663.928us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 7.000s 696.811us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 663.928us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 55.000s 4552.976us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 60441727316045294714517071369472127926354650970845589160628665670684986218735 86
UVM_INFO @ 10990151606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 57787088764598828078502190445356622450776627635335119705037043521254007585371 86
UVM_INFO @ 680770169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 92657675960366891531893084553323148161526307658813522736754348193880866853950 86
UVM_INFO @ 2639736040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 4228229070299204904867737557619393035019955170538638954416611756527412007054 86
UVM_INFO @ 1313968206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 15283873092119487206518017853643048581747911479363031287751328919613271463431 86
UVM_INFO @ 7297682332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 64357119780050170074674710273414721252559151946115832598508827075210586894453 86
UVM_INFO @ 709802250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 58711620787169654759383768837018318758826362878124272409902791647065409491944 86
UVM_INFO @ 686261113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 62827224644694969919522029766295949632751453266475743909761569487038896982796 86
UVM_INFO @ 2752246916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 94001681467935499213068705723799162839122048058483105559771208184981140581757 86
UVM_INFO @ 1384613642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 57458565545123928431438860330756255039569572036183518140761771604458686525580 86
UVM_INFO @ 1375233057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 70485033607885964636050835361954420218027487924238605360851528815213092278329 86
UVM_INFO @ 2748341126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 100768695730471317527521723041917389611961256612390221779302668639300957728090 86
UVM_INFO @ 944908466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 54332219383478586043273467402938880820728386069510964341575079907292885619631 86
UVM_INFO @ 1371431659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 88441580998375529711042841217338311954305516983971431644225280563455343461209 86
UVM_INFO @ 660285680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 56338551764336110191967772897886663102495493379735041684393600348388295580691 86
UVM_INFO @ 664249219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 80598043698699060577604441790335749549602460181334888885856213009962165309359 86
UVM_INFO @ 687281476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 20110509675031188688616780117418254092863215468580062507284762750183680893702 86
UVM_INFO @ 683953544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 99733045126256198306391758301427812141445540937005367585169476690268850190025 86
UVM_INFO @ 678017986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 68044263887560371022288885222579221474086672555746016546976129862568334572863 86
UVM_INFO @ 2791042142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 86709885939108491974593844759566726202432450588318031187359855348511482819725 86
UVM_INFO @ 673015021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 49379256346669914285040592618491737190888516787975381392691963133320054478457 86
UVM_INFO @ 2655080843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 67505570265590884234386065034149670527078542553964675133035034313085109881886 86
UVM_INFO @ 2290001009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 37698489928301801771791449610278791807062802379838789846336764660071398773530 86
UVM_INFO @ 1753908806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 111566546897520045813911638021859103957685303202303002116963715100856999609122 86
UVM_INFO @ 1346093450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---