Simulation Results: sram_ctrl/ret

 
27/06/2026 02:42:03 DVSim: v1.49.0 sha: 1134d70 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.46 %
  • code
  • 82.50 %
  • assert
  • 98.08 %
  • func
  • 96.80 %
  • block
  • 94.03 %
  • line
  • 95.21 %
  • branch
  • 89.83 %
  • toggle
  • 78.31 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 3.000s 183.592us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 20.132us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 1.000s 24.081us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 58.427us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 35.401us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 67.859us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 1.000s 24.081us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 35.401us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 9.000s 712.002us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 7.000s 358.734us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 13.000s 354.182us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 221.000s 7930.844us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 11.000s 559.502us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 23.000s 942.732us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 7.000s 729.911us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 19.000s 1393.720us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 3.000s 305.993us 8 8 100.00
sram_ctrl_partial_access_b2b 487.000s 337594.939us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 2.000s 102.439us 0 8 0.00
sram_ctrl_throughput_w_partial_write 2.000s 73.652us 0 8 0.00
sram_ctrl_throughput_w_readback 3.000s 133.772us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 17.000s 1035.130us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 2.000s 85.139us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 44.000s 5254.065us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 17.588us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 1948.982us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 1948.982us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 20.132us 1 1 100.00
sram_ctrl_csr_rw 1.000s 24.081us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 35.401us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 94.759us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 20.132us 1 1 100.00
sram_ctrl_csr_rw 1.000s 24.081us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 35.401us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 94.759us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 1112.532us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 5.000s 2887.798us 5 5 100.00
sram_ctrl_tl_intg_err 3.000s 620.154us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 2887.798us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 3.000s 620.154us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 17.000s 1035.130us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 17.000s 1035.130us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 1.000s 24.081us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 19.000s 1393.720us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 19.000s 1393.720us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 19.000s 1393.720us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 7.000s 729.911us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 2.000s 244.555us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 1112.532us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 2.000s 44.441us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 3.000s 183.592us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 3.000s 183.592us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 19.000s 1393.720us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 2887.798us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 7.000s 729.911us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 2887.798us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 2887.798us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 3.000s 183.592us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 2887.798us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 96.000s 2461.432us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 30168677892237847606070429678800350071393019842147469582968670103279392316749 86
UVM_INFO @ 102438996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 61720430398903947113944982122643442492907086946350925276531106260030694119924 86
UVM_INFO @ 50659141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 2257856011602678458936825406327997891500337923490933252804190383018519430732 86
UVM_INFO @ 27607640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 96670098293992211995795297601926556693128452106603428032034643857335009687626 86
UVM_INFO @ 73652028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 69003646265738728910633696726345137840807550976008257440088363653378391300913 86
UVM_INFO @ 57409451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 114230002517013524762114676414302255958069192205270342467861374073517603097212 86
UVM_INFO @ 243509410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 34283588066376726297502575967096975810349391594458470961266927019426631778837 86
UVM_INFO @ 45836666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 58465838080542355640975048652976477471323358119756623296843628818425424763673 86
UVM_INFO @ 36854435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 5946576833011498258401732420696191038561712852782466359537771837179459661498 86
UVM_INFO @ 32281496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 87853969411801829363080770402538306338605326824818126732555277971816322032182 86
UVM_INFO @ 44166992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 2022700105954393979181701627968760768023307693649904196384430003530107199082 86
UVM_INFO @ 44243051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 47445962878466134464437284767490816327770042981790587317642743776010328531417 86
UVM_INFO @ 44379473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 77720154327634790138024378226995760462399185859167647291777357791085288926925 86
UVM_INFO @ 25623008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 38704080810422058983725691395466945835686416944369303395574837754487352543974 86
UVM_INFO @ 70515977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 100792648393049464175709933638871165253700561308694282702047344523627624961998 86
UVM_INFO @ 24723478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 26065408616981780332468727023525790703458567031298269416795824975525168827465 86
UVM_INFO @ 110482449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 115614272251092260276924886506797606988664354681551791833245733521573454311840 86
UVM_INFO @ 28019239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 94271254365243368436763373656579724867176787248973601823556038265042288282086 86
UVM_INFO @ 31238072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 88770456761124625431419154180524689000806879375589144044056028672806633000184 86
UVM_INFO @ 78804187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 69475497523839613105760782943972233256403098662805867690043720162883947694395 86
UVM_INFO @ 118951950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 115427975168647366968941843467240627380156502713089344743170303657552287043314 86
UVM_INFO @ 137792666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 18531453805391617039951535850783388651379286611394216340272171278038654768265 86
UVM_INFO @ 133772079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 78280501007970675805514604684512000852681437780983363496070875282565096270030 86
UVM_INFO @ 32478978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 84749918042513479010781446133435507392984138676179216979524222497292325939547 86
UVM_INFO @ 115179796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---