Simulation Results

Simulation Results: sysrst_ctrl

27/06/2026 02:42:03 DVSim: v1.49.0 sha: 1134d70 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
94.35 %

code
98.32 %

assert
98.75 %

func
85.98 %

line
99.37 %

branch
99.41 %

cond
97.96 %

toggle
100.00 %

FSM
94.87 %

Validation stages

V1		97.67%
V2		97.60%
V2S		100.00%
V3		100.00%

42/43 passed

97.67 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	sysrst_ctrl_smoke	7.020s	2112.369us	10	10	100.00
input_output_inverted				10	10	100.00
	sysrst_ctrl_in_out_inverted	6.830s	2462.837us	10	10	100.00
combo_detect_ec_rst				4	5	80.00
	sysrst_ctrl_combo_detect_ec_rst	6.410s	2252.387us	4	5	80.00
combo_detect_ec_rst_with_pre_cond				5	5	100.00
	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	8.950s	2532.337us	5	5	100.00
csr_hw_reset				1	1	100.00
	sysrst_ctrl_csr_hw_reset	7.580s	4032.588us	1	1	100.00
csr_rw				5	5	100.00
	sysrst_ctrl_csr_rw	6.600s	2030.795us	5	5	100.00
csr_bit_bash				1	1	100.00
	sysrst_ctrl_csr_bit_bash	52.170s	41738.485us	1	1	100.00
csr_aliasing				1	1	100.00
	sysrst_ctrl_csr_aliasing	6.370s	2572.634us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	sysrst_ctrl_csr_mem_rw_with_rand_reset	4.020s	2070.252us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	sysrst_ctrl_csr_rw	6.600s	2030.795us	5	5	100.00
	sysrst_ctrl_csr_aliasing	6.370s	2572.634us	1	1	100.00

326/334 passed

97.60 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
combo_detect				25	25	100.00
	sysrst_ctrl_combo_detect	339.740s	177454.120us	25	25	100.00
combo_detect_with_pre_cond				92	100	92.00
	sysrst_ctrl_combo_detect_with_pre_cond	375.920s	166278.402us	92	100	92.00
auto_block_key_outputs				25	25	100.00
	sysrst_ctrl_auto_blk_key_output	463.340s	207672.913us	25	25	100.00
keyboard_input_triggered_interrupt				50	50	100.00
	sysrst_ctrl_edge_detect	596.690s	1138777.233us	50	50	100.00
pin_output_keyboard_inversion_control				10	10	100.00
	sysrst_ctrl_pin_override_test	8.340s	2513.719us	10	10	100.00
pin_input_value_accessibility				10	10	100.00
	sysrst_ctrl_pin_access_test	7.720s	2201.264us	10	10	100.00
ec_power_on_reset				10	10	100.00
	sysrst_ctrl_ec_pwr_on_rst	9.730s	3148.344us	10	10	100.00
flash_write_protect_output				10	10	100.00
	sysrst_ctrl_flash_wr_prot_out	8.820s	2609.397us	10	10	100.00
ultra_low_power_test				25	25	100.00
	sysrst_ctrl_ultra_low_pwr	346.010s	1016890.057us	25	25	100.00
sysrst_ctrl_feature_disable				2	2	100.00
	sysrst_ctrl_feature_disable	83.720s	41584.052us	2	2	100.00
stress_all				10	10	100.00
	sysrst_ctrl_stress_all	1079.170s	521175.955us	10	10	100.00
alert_test				10	10	100.00
	sysrst_ctrl_alert_test	7.290s	2008.597us	10	10	100.00
intr_test				10	10	100.00
	sysrst_ctrl_intr_test	6.540s	2014.085us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	sysrst_ctrl_tl_errors	9.030s	2043.216us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	sysrst_ctrl_tl_errors	9.030s	2043.216us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	sysrst_ctrl_csr_hw_reset	7.580s	4032.588us	1	1	100.00
	sysrst_ctrl_csr_rw	6.600s	2030.795us	5	5	100.00
	sysrst_ctrl_csr_aliasing	6.370s	2572.634us	1	1	100.00
	sysrst_ctrl_same_csr_outstanding	22.150s	10350.908us	5	5	100.00
tl_d_partial_access				12	12	100.00
	sysrst_ctrl_csr_hw_reset	7.580s	4032.588us	1	1	100.00
	sysrst_ctrl_csr_rw	6.600s	2030.795us	5	5	100.00
	sysrst_ctrl_csr_aliasing	6.370s	2572.634us	1	1	100.00
	sysrst_ctrl_same_csr_outstanding	22.150s	10350.908us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	sysrst_ctrl_sec_cm	74.010s	42008.463us	5	5	100.00
	sysrst_ctrl_tl_intg_err	110.030s	42465.601us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	sysrst_ctrl_tl_intg_err	110.030s	42465.601us	25	25	100.00

10/10 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				10	10	100.00
	sysrst_ctrl_stress_all_with_rand_reset	18.640s	7961.991us	10	10	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-*				2 test runs
	sysrst_ctrl_combo_detect_with_pre_cond	84583432013671715629343351628504052176812217005980899219641370187584743294672	682	UVM_INFO @ 37217424348 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x27 UVM_INFO @ 37217744348 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0xe UVM_INFO @ 37614364348 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2 UVM_INFO @ 37614364348 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3
	sysrst_ctrl_combo_detect_with_pre_cond	83730093194666255778830365532741986693522417754088765057444468885268646721990	680	UVM_INFO @ 24529061147 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0 UVM_INFO @ 24704061147 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 24724061147 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_INFO @ 34796547275 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x27
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [] vs [*])				2 test runs
	sysrst_ctrl_combo_detect_with_pre_cond	95597251692224814208337662847385096970517166579896629306730414443356000169016	692	UVM_ERROR @ 28443783956 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 28443783956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_combo_detect_with_pre_cond	66682287513683759800911642962966457118266350384037372672980584113100591092648	667	UVM_INFO @ 14312710107 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 14332710107 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_INFO @ 24445323630 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2a UVM_INFO @ 24445448631 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x28
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value:				1 test run
	sysrst_ctrl_combo_detect_ec_rst	34735651011418799296962933756863853329214525043557355758896705561697266861816	656	UVM_INFO @ 2404985372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-*				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	106570978181440749035297614588684689881240311159739097639947021579302400315447	676	UVM_INFO @ 24572478162 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0 UVM_INFO @ 24797478162 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 24817478162 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_INFO @ 34844991202 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x31
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(4) +/-*				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	83599649074498084442853683989400946674496953174218827995863199756250251634458	701	UVM_INFO @ 58985640150 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x26 UVM_INFO @ 58985832918 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x32 UVM_INFO @ 59572877465 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0 UVM_INFO @ 59573100630 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (* [] vs [*])				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	94657768195798153048389282025775618433646629522944554279622315224410009981886	687	UVM_INFO @ 36959271909 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x30 UVM_INFO @ 36959480239 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x12 UVM_INFO @ 37264382862 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0 UVM_INFO @ 37264382862 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(5) +/-*				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	58355260431319781655278451964505686948443085499980442343903687729947470235823	665	UVM_ERROR @ 13042349387 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(9) vs exp(5) +/-4 UVM_INFO @ 13042349387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---