Simulation Results: adc_ctrl

 
04/07/2026 02:41:51 DVSim: v1.49.0 sha: 98a020b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 67.55 %
  • code
  • 96.24 %
  • assert
  • 92.71 %
  • func
  • 13.69 %
  • line
  • 98.96 %
  • branch
  • 97.59 %
  • cond
  • 87.59 %
  • toggle
  • 99.76 %
  • FSM
  • 97.30 %
Validation stages
V1
100.00%
V2
50.85%
V2S
100.00%
V3
30.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
adc_ctrl_smoke 15.670s 5903.506us 10 10 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.850s 752.489us 1 1 100.00
csr_rw 5 5 100.00
adc_ctrl_csr_rw 2.300s 541.774us 5 5 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 53.940s 22755.104us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.160s 837.628us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 2.260s 440.380us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
adc_ctrl_csr_rw 2.300s 541.774us 5 5 100.00
adc_ctrl_csr_aliasing 2.160s 837.628us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 10 0.00
adc_ctrl_filters_polled 1.880s 499.046us 0 10 0.00
filters_polled_fixed 0 10 0.00
adc_ctrl_filters_polled_fixed 1.890s 513.076us 0 10 0.00
filters_interrupt 0 10 0.00
adc_ctrl_filters_interrupt 1.810s 341.126us 0 10 0.00
filters_interrupt_fixed 0 10 0.00
adc_ctrl_filters_interrupt_fixed 2.080s 480.723us 0 10 0.00
filters_wakeup 0 10 0.00
adc_ctrl_filters_wakeup 2.180s 500.288us 0 10 0.00
filters_wakeup_fixed 0 10 0.00
adc_ctrl_filters_wakeup_fixed 1.860s 384.344us 0 10 0.00
filters_both 0 10 0.00
adc_ctrl_filters_both 1.630s 306.542us 0 10 0.00
clock_gating 0 10 0.00
adc_ctrl_clock_gating 2.110s 524.696us 0 10 0.00
poweron_counter 10 10 100.00
adc_ctrl_poweron_counter 13.020s 5126.869us 10 10 100.00
lowpower_counter 10 10 100.00
adc_ctrl_lowpower_counter 81.650s 42970.434us 10 10 100.00
fsm_reset 10 10 100.00
adc_ctrl_fsm_reset 205.350s 110505.995us 10 10 100.00
stress_all 3 10 30.00
adc_ctrl_stress_all 105.460s 172106.666us 3 10 30.00
alert_test 10 10 100.00
adc_ctrl_alert_test 2.090s 466.674us 10 10 100.00
intr_test 10 10 100.00
adc_ctrl_intr_test 2.030s 504.714us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
adc_ctrl_tl_errors 3.800s 1014.487us 25 25 100.00
tl_d_illegal_access 25 25 100.00
adc_ctrl_tl_errors 3.800s 1014.487us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
adc_ctrl_csr_hw_reset 2.850s 752.489us 1 1 100.00
adc_ctrl_csr_rw 2.300s 541.774us 5 5 100.00
adc_ctrl_csr_aliasing 2.160s 837.628us 1 1 100.00
adc_ctrl_same_csr_outstanding 11.190s 4323.503us 5 5 100.00
tl_d_partial_access 12 12 100.00
adc_ctrl_csr_hw_reset 2.850s 752.489us 1 1 100.00
adc_ctrl_csr_rw 2.300s 541.774us 5 5 100.00
adc_ctrl_csr_aliasing 2.160s 837.628us 1 1 100.00
adc_ctrl_same_csr_outstanding 11.190s 4323.503us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
adc_ctrl_sec_cm 18.450s 7840.782us 5 5 100.00
adc_ctrl_tl_intg_err 24.140s 8501.167us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
adc_ctrl_tl_intg_err 24.140s 8501.167us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
adc_ctrl_stress_all_with_rand_reset 15.470s 6261.093us 3 10 30.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 94 test runs
adc_ctrl_filters_polled 11851452747597023018894259697721316960196626158613241058651129357970985284722 386
UVM_INFO @ 516991774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 103701258844535987259840902245763452472900782526238395984036739261599193503250 386
UVM_INFO @ 368027101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 47057181562777422813666007206830106107940586260631865996672171997867273604641 386
UVM_INFO @ 269799178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 10800635880475385742657472436481859749420074147949359359280093712196409797095 386
UVM_INFO @ 373856789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 33430562056014529711032839805571660648041416173667312057759911876108900390526 386
UVM_INFO @ 481386932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 64837418860583238073292855107263461414846459564560664948881445680451761825841 386
UVM_INFO @ 286217812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 54622610621712293190349194536426460888745532648948393277025145553844000459448 386
UVM_INFO @ 524696008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 64148077330790556418387636053742687518298526765081111854111128057416051695715 386
UVM_INFO @ 512184517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 47774081933620081755631074102979470976005935961529744741700690487403992947387 399
UVM_INFO @ 5090390009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 28281790703249073405838854974087245502480926500842742198120192279266474630007 386
UVM_INFO @ 422763499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 90497052551474047586759851629621126365955033609610448208407802430543388625341 386
UVM_INFO @ 331301901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 28354466997992094755686140058052098049658491048905666542978644368520086445070 386
UVM_INFO @ 431103700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 79898930492556433224072204830479485916784835499540272560489319807105636420137 386
UVM_INFO @ 338795380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 9389475178137750693685613128336784922178637451472206116993103139126694829074 386
UVM_INFO @ 500288492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 14815243145977276444264917897764762236287944814585869948773597577089645829869 386
UVM_INFO @ 332236344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 22457537833529650109511028012509214118124423480602805041479768397425149680470 386
UVM_INFO @ 399979781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 89296270277681288180645713632405612665085789956611168907353115016903776992043 386
UVM_INFO @ 294217693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 2193020398234830288628875529982243021094797897090619508504407948588850393130 399
UVM_INFO @ 872854286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 15313326559807795290479441836220345408865673634685282325826097862835052601735 387
UVM_INFO @ 735968353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 113694331849386165114893381177900662720193079676640116527339823283177920353361 386
UVM_INFO @ 288529164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 58939418954967772307964435430938291745148971806915456685825828940852849857904 386
UVM_INFO @ 381342002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 13156328436992791494069732862318703934070227933805079256419985970859993480595 386
UVM_INFO @ 323567575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 40858137695989858789681103628061155762309678913612701791433304624740823688660 386
UVM_INFO @ 302519040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 88117323693522995530667285665624836648472882235842667522248854902728072262667 386
UVM_INFO @ 439957946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 43791918469489615751574296603998880033653606845674755178635934221266022072343 386
UVM_INFO @ 514894489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 107321918113917275224283810076021468658740474489520603192135585398667730079538 386
UVM_INFO @ 320699396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 14713043877556774949504369883538618059030078570034675582342913606089705143032 386
UVM_INFO @ 306541874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 93133856751014501681319093809377863465972629657065723856084096688762603558611 392
UVM_INFO @ 740448330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 30422887996272511163292992802783681751686764632533280558433780213456674095720 400
UVM_INFO @ 1304375196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 26828893598990620404292666222067889308842885691011740208615497715434074250322 386
UVM_INFO @ 454672254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 114626991810568359509088264008375640507836018005609508588452125078366957489788 386
UVM_INFO @ 365544773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 9002359579734236873833920797747423492619772453218089600338983561342983402773 386
UVM_INFO @ 378970732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 112642372178322758131645999740943271307912850719541938632947584960801828514253 386
UVM_INFO @ 505002611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 115453281302012070021426023378983933705756943088485305904214886038668832289639 386
UVM_INFO @ 400114891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 13063361172609815151429140781670322730811131944808617376258879502270687374043 386
UVM_INFO @ 397705497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 112972343187426419056426504210865409057952734089306040869857728608900229621509 386
UVM_INFO @ 500836025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 4482300575139413776122158613983088542902863518024804804611168177731142689705 386
UVM_INFO @ 377327201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 109023439878051497525697096981026777757051013328027764654792222817894561194823 424
UVM_INFO @ 4306810269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 15244953369271828052026980000224862798745306602711278610816140561869858166187 386
UVM_INFO @ 499046243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 81872891381331374302665731870404774330412908005692710229481604433484010719201 386
UVM_INFO @ 345541870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 95277786605580404987408025955645309790075736405607342966527536193901783841456 386
UVM_INFO @ 415459014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 10112636269374200302010802273805720641438048276704104372385302864390022792569 386
UVM_INFO @ 480722512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 99922436954029242732979910583645612925228433686251840616468528798195715649960 386
UVM_INFO @ 384881677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 74619190671738043459404294435380977024270205199758353806031079371042056003550 386
UVM_INFO @ 478185367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 97792485192720430885609272333514966317422215394708626490429205272466806790953 386
UVM_INFO @ 388259921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 40997864510801641698394439901567831349047053309988072768628406825978711201535 386
UVM_INFO @ 523516138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 83993367616920089020792501854628783572367526740547154732925704540718505167874 410
UVM_INFO @ 2989925439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 105656169162522905015620428904517992899921005093323027702176994747550116955524 386
UVM_INFO @ 421222746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 107696646751682108901522833086350403355074372407382520042583317181576488456545 386
UVM_INFO @ 544950252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 61119331699544221137430623167059930659697181721447100652497860654874624376791 386
UVM_INFO @ 440712697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 61443816980041085061007713769866874385634788366599318180128493635569713746996 386
UVM_INFO @ 500821238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 104120108877799518888454802954783863786208918035986463318238008087914534003737 386
UVM_INFO @ 439389504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 52295499152146018372327576252816619794714367833178311923321414712744700941761 386
UVM_INFO @ 503135351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 30759173256823948064767883506303750391521571341276900099707334180197041674806 386
UVM_INFO @ 281915361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 90414440357872090916265916998804514328729487798840714706431206234494976244923 386
UVM_INFO @ 499630880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 72716828197924941707179692373315773068667994774360103093537871398119859636685 386
UVM_INFO @ 304374576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 74083870256724371763622692078156982866284660204943306821847770348549682358111 386
UVM_INFO @ 350428001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 26382492801924688186503973024961100581467068764518227950555880157660406287817 386
UVM_INFO @ 397498978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 23317758263575625663019091583069588671092080373978424612600995347591098096872 386
UVM_INFO @ 438859248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 84084579361460032605584820147655453296018269934184789593822146658362308808384 386
UVM_INFO @ 411243293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 10042841834990578484837721660749027832217715147702432784434251937165235506361 386
UVM_INFO @ 281998449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 55117208731363536671094542589137471840982576203796144535365787858842262004564 386
UVM_INFO @ 487103857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 72440762800712338920603951023328859786981123924668881138244788790191158314895 386
UVM_INFO @ 447081986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 39782958744030121087056207011748803307890218042723761129515076505837624144183 403
UVM_INFO @ 760109206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 67187295740521422401518965501540987946978314225306942939050541727977612889835 387
UVM_INFO @ 877288884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 61514726938815327692806286193829861245112130877610872971762257354705537236776 386
UVM_INFO @ 359123758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 107098508134569487348255306613772408149674106627129424814078703551653279481193 386
UVM_INFO @ 513076471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 59109813607028125203620108049554565973237459456413470173511589707900246840099 386
UVM_INFO @ 341125744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 101811305754864940348464337898500691045185097416924614922024537561383622331594 386
UVM_INFO @ 312945540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 46877569188188138555034496959967388160354085323536911558542146439053695639630 386
UVM_INFO @ 497933484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 59658655693785259888083504958337816936158183002300500242286891534402831804495 386
UVM_INFO @ 384343809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 98526934247863690693659556186454147174403773120370436592925531507264116900187 386
UVM_INFO @ 279704466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 99648290174350296210329365348140561298524206851496753498208680634290592617798 386
UVM_INFO @ 460568951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 112317914619949785277527143315059253886779701699036396292336815272026071189691 392
UVM_INFO @ 855306946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 63372628329939589530643463437274828815553338885433491552146780550841313264927 497
UVM_INFO @ 37387852292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 62208317545511055604630894356613658266646505980914841641079885371363249504054 386
UVM_INFO @ 516124931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 76768366281097437947672190667000377299510394728443293154695157048700371415655 386
UVM_INFO @ 465757309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 12104000567486940177583688165584835582811962022450371495975786110750591735947 386
UVM_INFO @ 323263921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 102310976222926724724099136044840937695994717300470328606656360474622873058856 386
UVM_INFO @ 461992185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 75387573809341154376168899164960139559877268993291785324062188903741396597003 386
UVM_INFO @ 404817980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 80293543430964216131924668751032799460186209944106456862423301705779301155282 386
UVM_INFO @ 407625147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 36547657114839556973960269493627151235348813967601945876246024071493709059135 386
UVM_INFO @ 422039613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 65580408378252892060982127369088162047380101618537872817614070234546932912456 386
UVM_INFO @ 527534753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 4490213423865418800386281338420763172521350953005391927140417600693455765583 400
UVM_INFO @ 1413417736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 43185031901416212104440308524545065566688405263018045850122210289384060851838 386
UVM_INFO @ 352654523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 84646024124981307619453741600621713986213636013472503975338890565085903075551 386
UVM_INFO @ 461322391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 22892522537760924035306013182973194871189117600575880444232095414917681883666 386
UVM_INFO @ 317766679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 72382523390535457302624733351327824370412027193475259895320577543509243507064 386
UVM_INFO @ 441271058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 108109949191662461134419867826463294839090993008815162097812604222180139143365 386
UVM_INFO @ 428465053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 79099762231137494569390157807136458629396872844739063265135425941552648876891 386
UVM_INFO @ 399622827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 68149137284848130692686856688908468365566104260765331165180358309421335365109 386
UVM_INFO @ 485071192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 8415817623569396133769066651427258165213006505898300737996612382584862578216 386
UVM_INFO @ 334782011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 83001926852346241313964044021007650657339770500464244240711833181840206350837 399
UVM_INFO @ 766879320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 102289787406433250480475199845232151634759834193406402873614959246016288793132 389
UVM_INFO @ 6359831670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---