| V1 |
|
100.00% |
| V2 |
|
88.36% |
| V2S |
|
98.54% |
| V3 |
|
40.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 62.540s | 2015.217us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 4.420s | 117.823us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| alert_handler_csr_rw | 6.790s | 130.034us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 235.040s | 4517.968us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 194.230s | 9082.919us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 11.040s | 306.763us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| alert_handler_csr_rw | 6.790s | 130.034us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 194.230s | 9082.919us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 25 | 25 | 100.00 | |||
| alert_handler_esc_alert_accum | 314.050s | 24677.755us | 25 | 25 | 100.00 | |
| esc_timeout | 50 | 50 | 100.00 | |||
| alert_handler_esc_intr_timeout | 75.960s | 6499.197us | 50 | 50 | 100.00 | |
| entropy | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 2579.670s | 668229.102us | 25 | 25 | 100.00 | |
| sig_int_fail | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 60.960s | 1048.153us | 50 | 50 | 100.00 | |
| clk_skew | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 62.540s | 2015.217us | 10 | 10 | 100.00 | |
| random_alerts | 10 | 10 | 100.00 | |||
| alert_handler_random_alerts | 61.140s | 6484.234us | 10 | 10 | 100.00 | |
| random_classes | 50 | 50 | 100.00 | |||
| alert_handler_random_classes | 77.460s | 7807.507us | 50 | 50 | 100.00 | |
| ping_timeout | 15 | 50 | 30.00 | |||
| alert_handler_ping_timeout | 492.380s | 11851.576us | 15 | 50 | 30.00 | |
| lpg | 97 | 100 | 97.00 | |||
| alert_handler_lpg | 2987.480s | 71424.379us | 47 | 50 | 94.00 | |
| alert_handler_lpg_stub_clk | 2883.780s | 889391.042us | 50 | 50 | 100.00 | |
| stress_all | 49 | 50 | 98.00 | |||
| alert_handler_stress_all | 3473.560s | 627529.967us | 49 | 50 | 98.00 | |
| alert_handler_entropy_stress_test | 0 | 20 | 0.00 | |||
| alert_handler_entropy_stress | 30.630s | 1457.408us | 0 | 20 | 0.00 | |
| alert_handler_alert_accum_saturation | 20 | 20 | 100.00 | |||
| alert_handler_alert_accum_saturation | 5.070s | 53.865us | 20 | 20 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| alert_handler_intr_test | 2.300s | 15.634us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 24.530s | 4210.977us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 24.530s | 4210.977us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 4.420s | 117.823us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 6.790s | 130.034us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 194.230s | 9082.919us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 45.360s | 2194.398us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 4.420s | 117.823us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 6.790s | 130.034us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 194.230s | 9082.919us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 45.360s | 2194.398us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 323.750s | 31817.358us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 323.750s | 31817.358us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 323.750s | 31817.358us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 323.750s | 31817.358us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 1047.410s | 15555.871us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| alert_handler_sec_cm | 27.420s | 549.167us | 5 | 5 | 100.00 | |
| alert_handler_tl_intg_err | 75.970s | 1278.761us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| alert_handler_tl_intg_err | 75.970s | 1278.761us | 25 | 25 | 100.00 | |
| sec_cm_config_shadow | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 323.750s | 31817.358us | 20 | 20 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 62.540s | 2015.217us | 10 | 10 | 100.00 | |
| sec_cm_alert_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 62.540s | 2015.217us | 10 | 10 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 62.540s | 2015.217us | 10 | 10 | 100.00 | |
| sec_cm_class_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 62.540s | 2015.217us | 10 | 10 | 100.00 | |
| sec_cm_alert_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 60.960s | 1048.153us | 50 | 50 | 100.00 | |
| sec_cm_lpg_intersig_mubi | 47 | 50 | 94.00 | |||
| alert_handler_lpg | 2987.480s | 71424.379us | 47 | 50 | 94.00 | |
| sec_cm_esc_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 60.960s | 1048.153us | 50 | 50 | 100.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 2579.670s | 668229.102us | 25 | 25 | 100.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 2579.670s | 668229.102us | 25 | 25 | 100.00 | |
| sec_cm_esc_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 27.420s | 549.167us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 27.420s | 549.167us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 27.420s | 549.167us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 27.420s | 549.167us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 27.420s | 549.167us | 5 | 5 | 100.00 | |
| sec_cm_accu_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 27.420s | 549.167us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 27.420s | 549.167us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 27.420s | 549.167us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 27.420s | 549.167us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 4 | 10 | 40.00 | |||
| alert_handler_stress_all_with_rand_reset | 297.680s | 4529.138us | 4 | 10 | 40.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | 31 test runs | |||
| alert_handler_ping_timeout | 10191965853819332882119596239408110886134970710936795217455990441526300500349 | 90 |
UVM_INFO @ 1961753211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 78575648815998325349959510067608085893328858746984157438775023562152120659683 | 114 |
UVM_INFO @ 9054473957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 17457811174714837676045045514657457783598875399115248717820816718609345933610 | 87 |
UVM_INFO @ 759416350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 47772580340546173612350642278399964110751926452146377078504791838859230768538 | 108 |
UVM_INFO @ 5855278105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 38763420734988781807025172500389354011098168909054836180384435832282736574496 | 84 |
UVM_INFO @ 4771155877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 4841047372319690818685754079712702561454675747255481456698848295224319982094 | 93 |
UVM_INFO @ 19856771599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 38926076329023082330435546947053639092070922699231284053116098974723014914685 | 107 |
UVM_INFO @ 17272962740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 9320546694760716987979407711571884537091926044011511812588961492764665534684 | 108 |
UVM_INFO @ 10796270713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 95905425581687835055806991369656355334729900774882663328855028642317078379238 | 86 |
UVM_INFO @ 2783159564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 23020682412463588611484353614785479263492320742861407200059207704201291441432 | 84 |
UVM_INFO @ 4768515936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 60512223449304820905555603547164486481289543857931596922600658155147947755115 | 99 |
UVM_INFO @ 3137212900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 37119389373762763770557125319514621052088061420865959866347219859768388444241 | 90 |
UVM_INFO @ 1565220240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 61964592659463637442846628839157371502991849807244628429323065638507131282323 | 87 |
UVM_INFO @ 2427253575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 82590286145285459053779060112965685154160287409190821639833519233032520134991 | 84 |
UVM_INFO @ 5010878114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 64317594346286418723252371249805497193302792956327059791215059519338315921805 | 123 |
UVM_INFO @ 26784455585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 31772030551205045008287690012054743644666183778499613960605972610505728289205 | 87 |
UVM_INFO @ 2351879454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 53742795760563950097892709218566707369649952151900260607710247176669828802009 | 106 |
UVM_INFO @ 18925636122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 66348278020536000401094726840768208395699426442712132457341146131216156147117 | 96 |
UVM_INFO @ 5201019832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 99983245656700034860336071332842907842383341501859615150668320294022688585223 | 157 |
UVM_INFO @ 14538960449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 36940476100789324615555285823585909705482833361002590968604585160490100786583 | 132 |
UVM_INFO @ 31221092770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 25284225873594902627147168323249098638943777380677288940786962015068438013084 | 90 |
UVM_INFO @ 11268800790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 30885352690797529196604649097626271463608425155296739385902813198594593927910 | 123 |
UVM_INFO @ 41040367294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 40425781398914152719049185023318517147240173499121533022060280031251703664874 | 112 |
UVM_INFO @ 36194381915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_lpg | 19709103226301060240816497604168828494277361200024676258497871233603072401465 | 80 |
UVM_INFO @ 18390792110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 89910172782586598129484183616718976524269060078531270520952951824213139606580 | 87 |
UVM_INFO @ 4301991722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 53418885657664690439215094395113579600592382584172581802650082228980307875091 | 135 |
UVM_INFO @ 43448801027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 45763844941814928034464166366957681374843820443447358514923079514469750418622 | 84 |
UVM_INFO @ 3711516093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 29614470303997004184062955188744424809752476413719713413407141895693950051768 | 99 |
UVM_INFO @ 4962477654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 95275545486699951657718408943102504210942108532895962725560329367838038168302 | 96 |
UVM_INFO @ 1791847941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 102594030037180906754230451604504546005550034464024101725616849763695283782963 | 105 |
UVM_INFO @ 4995939441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 60188747650728855314430489582645445862231444600724200784823362041193299227985 | 90 |
UVM_INFO @ 2306007254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 20 test runs | |||
| alert_handler_entropy_stress | 18891016295525756576444614357256976947368665785895376009032272631225755447592 | 202 |
UVM_INFO @ 813846802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 23416756670584635969722665927531496228586967965315561956243805763309411552523 | 134 |
UVM_INFO @ 1426057286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 105196413486274025002369062217587765725042402992860832191217715370633839370602 | 184 |
UVM_INFO @ 133523544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 108141288415913835405723941866666134291294436525445907290423854726312395747361 | 194 |
UVM_INFO @ 69982534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 35259540232295458822071059581537892207885833418790829225340026456285517708115 | 160 |
UVM_INFO @ 504575048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 40564612110991938394500835172494437143293737680996799040588658837705605902301 | 196 |
UVM_INFO @ 408798978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 94401057012919355454220018999250833199521791982326819472127651531844405860948 | 194 |
UVM_INFO @ 356460237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 45394520548739449073438158070336519760727383769199140178188426798198050795042 | 140 |
UVM_INFO @ 290219936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 56708424236642188221579061673274267689093295240485869377008453692715956555184 | 172 |
UVM_INFO @ 75284225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 59762833392826511297984990178942811050346451136087834445781952483181340584380 | 172 |
UVM_INFO @ 322305920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 64164389494392762726806655756153357498748696489784246262252501482036865041325 | 170 |
UVM_INFO @ 117727791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 45215877449148818023218946299404795453128172989927683845722035481082539031921 | 198 |
UVM_INFO @ 892847766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 57350062112141452320067042218719173200394324182442198943369509431616752400070 | 190 |
UVM_INFO @ 133284831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 92369377714527803549003483597554246337506666563637696198580430210097714104632 | 174 |
UVM_INFO @ 408135699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 80307013272568015883601464389261813570580459327312674133744387877312473894414 | 190 |
UVM_INFO @ 357315456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 60170560009489789923388292664834974691220904195264248023399661708236927904111 | 174 |
UVM_INFO @ 785962767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 100164542132513552412973813338306409005392015067193103512031688682049627450449 | 202 |
UVM_INFO @ 232790659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 70737604854087581391618627690930352472398296784429610734354729548536845912813 | 194 |
UVM_INFO @ 1457407826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 10620354225055974976950802678016711048993433405879805713002736408103413339226 | 182 |
UVM_INFO @ 46964537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 94562981681029539884525230632150836569089903525737001127292240015810334899986 | 140 |
UVM_INFO @ 720078609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 6 test runs | |||
| alert_handler_stress_all_with_rand_reset | 8477936405723448149535937470241216948566971954223444564264075037809608726991 | 121 |
UVM_INFO @ 8662611882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 8343180970489034493695309407143831471245461849530459409482923711892016414795 | 83 |
UVM_INFO @ 318883257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 57633370723215852696942246099046124126124851861933946882886249632183964104246 | 171 |
UVM_INFO @ 3196597732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 44070640658092226046265347625224443822186874868510888544551606762890411737366 | 143 |
UVM_INFO @ 11594687438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 34614561677273650485605883101294550439892736183598108409412022135506732388070 | 87 |
UVM_INFO @ 317182860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 19625013056777965479461275479647667022607683078915475497832740342275534262393 | 82 |
UVM_INFO @ 205264841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. | 5 test runs | |||
| alert_handler_ping_timeout | 77442588413652206685173628358209296964830146672262169918541539486048559646893 | 80 |
UVM_INFO @ 1184451769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 64608239897777752715568999311339104875999481212810322645744931613984054981398 | 80 |
UVM_INFO @ 1366192711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 108094945814974497164987771496379074465388655927897971603609243645837422901584 | 80 |
UVM_INFO @ 344579051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 114331308433849895632523625946418924108643019125921298141115991332242314176424 | 80 |
UVM_INFO @ 572900326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_lpg | 67704389686016811561699525759099226265838040957920597049772574874434127140099 | 80 |
UVM_INFO @ 11553047475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalEscPingFail) | 1 test run | |||
| alert_handler_ping_timeout | 53569729414091874360947331830738822399882645672255018542113933626112297873699 | 84 |
UVM_INFO @ 1151327830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| UVM_ERROR (cip_base_vseq.sv:858) [alert_handler_sig_int_fail_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) | 1 test run | |||
| alert_handler_stress_all | 75531398919098610918760272566528766434598226438997826580866860365689567965442 | 96 |
UVM_INFO @ 69406364212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_state | 1 test run | |||
| alert_handler_lpg | 27764277160668291508861055647809813625829638185495887054133183348778431967619 | 81 |
UVM_INFO @ 3778562837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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