Simulation Results: clkmgr

 
04/07/2026 02:41:51 DVSim: v1.49.0 sha: 98a020b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.31 %
  • code
  • 98.79 %
  • assert
  • 96.33 %
  • func
  • 87.82 %
  • line
  • 99.24 %
  • branch
  • 98.95 %
  • cond
  • 95.77 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
79.31%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
clkmgr_smoke 1.570s 125.544us 10 10 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.990s 17.227us 1 1 100.00
csr_rw 5 5 100.00
clkmgr_csr_rw 1.470s 226.205us 5 5 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 6.320s 459.636us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 2.070s 190.317us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.970s 107.860us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
clkmgr_csr_rw 1.470s 226.205us 5 5 100.00
clkmgr_csr_aliasing 2.070s 190.317us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 10 10 100.00
clkmgr_peri 1.130s 39.297us 10 10 100.00
trans_enables 10 10 100.00
clkmgr_trans 1.620s 155.306us 10 10 100.00
extclk 10 10 100.00
clkmgr_extclk 1.630s 332.961us 10 10 100.00
clk_status 10 10 100.00
clkmgr_clk_status 1.400s 140.291us 10 10 100.00
jitter 10 10 100.00
clkmgr_smoke 1.570s 125.544us 10 10 100.00
frequency 10 10 100.00
clkmgr_frequency 12.710s 2361.590us 10 10 100.00
frequency_timeout 10 10 100.00
clkmgr_frequency_timeout 15.480s 1820.841us 10 10 100.00
frequency_overflow 10 10 100.00
clkmgr_frequency 12.710s 2361.590us 10 10 100.00
stress_all 10 10 100.00
clkmgr_stress_all 63.740s 10512.181us 10 10 100.00
alert_test 10 10 100.00
clkmgr_alert_test 2.170s 292.901us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
clkmgr_tl_errors 10.510s 2026.614us 25 25 100.00
tl_d_illegal_access 25 25 100.00
clkmgr_tl_errors 10.510s 2026.614us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
clkmgr_csr_hw_reset 0.990s 17.227us 1 1 100.00
clkmgr_csr_rw 1.470s 226.205us 5 5 100.00
clkmgr_csr_aliasing 2.070s 190.317us 1 1 100.00
clkmgr_same_csr_outstanding 2.000s 275.226us 5 5 100.00
tl_d_partial_access 12 12 100.00
clkmgr_csr_hw_reset 0.990s 17.227us 1 1 100.00
clkmgr_csr_rw 1.470s 226.205us 5 5 100.00
clkmgr_csr_aliasing 2.070s 190.317us 1 1 100.00
clkmgr_same_csr_outstanding 2.000s 275.226us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 16 30 53.33
clkmgr_sec_cm 2.460s 208.028us 1 5 20.00
clkmgr_tl_intg_err 44.620s 10126.500us 15 25 60.00
shadow_reg_update_error 11 20 55.00
clkmgr_shadow_reg_errors 1016.980s 200000.000us 11 20 55.00
shadow_reg_read_clear_staged_value 11 20 55.00
clkmgr_shadow_reg_errors 1016.980s 200000.000us 11 20 55.00
shadow_reg_storage_error 11 20 55.00
clkmgr_shadow_reg_errors 1016.980s 200000.000us 11 20 55.00
shadowed_reset_glitch 11 20 55.00
clkmgr_shadow_reg_errors 1016.980s 200000.000us 11 20 55.00
shadow_reg_update_error_with_csr_rw 14 20 70.00
clkmgr_shadow_reg_errors_with_csr_rw 1026.660s 200000.000us 14 20 70.00
sec_cm_bus_integrity 15 25 60.00
clkmgr_tl_intg_err 44.620s 10126.500us 15 25 60.00
sec_cm_meas_clk_bkgn_chk 10 10 100.00
clkmgr_frequency 12.710s 2361.590us 10 10 100.00
sec_cm_timeout_clk_bkgn_chk 10 10 100.00
clkmgr_frequency_timeout 15.480s 1820.841us 10 10 100.00
sec_cm_meas_config_shadow 11 20 55.00
clkmgr_shadow_reg_errors 1016.980s 200000.000us 11 20 55.00
sec_cm_idle_intersig_mubi 10 10 100.00
clkmgr_idle_intersig_mubi 1.800s 205.835us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
clkmgr_lc_ctrl_intersig_mubi 1.390s 92.147us 10 10 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.290s 56.410us 10 10 100.00
sec_cm_clk_handshake_intersig_mubi 9 10 90.00
clkmgr_clk_handshake_intersig_mubi 1.340s 69.184us 9 10 90.00
sec_cm_div_intersig_mubi 10 10 100.00
clkmgr_div_intersig_mubi 2.370s 407.117us 10 10 100.00
sec_cm_jitter_config_mubi 5 5 100.00
clkmgr_csr_rw 1.470s 226.205us 5 5 100.00
sec_cm_idle_ctr_redun 1 5 20.00
clkmgr_sec_cm 2.460s 208.028us 1 5 20.00
sec_cm_meas_config_regwen 5 5 100.00
clkmgr_csr_rw 1.470s 226.205us 5 5 100.00
sec_cm_clk_ctrl_config_regwen 5 5 100.00
clkmgr_csr_rw 1.470s 226.205us 5 5 100.00
prim_count_check 1 5 20.00
clkmgr_sec_cm 2.460s 208.028us 1 5 20.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 10 10 100.00
clkmgr_regwen 8.020s 1426.682us 10 10 100.00
stress_all_with_rand_reset 10 10 100.00
clkmgr_stress_all_with_rand_reset 116.270s 25585.293us 10 10 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 13 test runs
clkmgr_shadow_reg_errors 23330975758566546437215285258523179279603335050083786598060470961172423389945 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 59431370013982077485354728598022073286519038696169266242295511969939203512598 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 30059798502346981363508063822603188925194547804729172041575361822920055674441 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 38930000138665676796695391029363955906504008031611412060377062160418528661419 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 33505815613703949299320163083228839069380417144281474027244558727849963014728 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 16792356783140011303575955861179891423513013751813741902978084310850516572521 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 100582634602477376333586469980698857842985319072978036504650128694116660047134 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 51579000147959284685102295717782199514722064819961316175669811397829330864770 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 3759616450723725137912182696519398610036545299044740306892386428110114472634 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 91829916171361352906562467391023989117202922252474197903009317234286501487875 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 99621196295384407175133913102478831911117380012086138822070828198254129072498 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 32169606883878582784865250455134562414953364195162421737767887922772247967727 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 104584067698409986603726287708458080290521970273853348875624853305839655906375 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 10 test runs
clkmgr_tl_intg_err 34367517460748073637047976245974793512312523902267590172667423720846520653654 118
UVM_INFO @ 10073913820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 3094299035139808233538609629613667105922360184691951945711577422127899549131 109
UVM_INFO @ 10294704175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 48587718105350573304265389520829297416038752564693126418508904115291255352718 89
UVM_INFO @ 10022993460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 115503105702484371727984310725821069759267520517085941130845205467679637424083 219
UVM_INFO @ 10126500461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 23118502033336958583570764006481699459645531306986738814439047257811236083046 113
UVM_INFO @ 10027084443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 19958243381003250595570059665507605050524258377425758478605581026965056848443 96
UVM_INFO @ 10015185913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 102481848421875966032489082839063523275886319865654871922243233036889823732973 122
UVM_INFO @ 10165697678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 10287716175955528090702879340242043073090132034485664257230020450251115742460 256
UVM_INFO @ 10422434399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 47413415364799091660499767128970714958065831677004349680155199253061516407469 154
UVM_INFO @ 10167848013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 89784730103920825822360681505275139198346497646922252067394466588986971702706 151
UVM_INFO @ 10178996299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 4 test runs
clkmgr_sec_cm 56026662859555647306799665783185070838954030512555099096114375308749731696771 120
UVM_INFO @ 76125404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 111362940023148630397957656991065564599546007449514597330662319073928028128729 77
UVM_INFO @ 2079701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 53700077568475950792435850515167886642279745687899613152208690711572319757858 80
UVM_INFO @ 6717374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 15164430595392601089493153692499618157004756992399596657679860954136164427586 78
UVM_INFO @ 1334819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq__shadow_reg_errors.svh:332) [clkmgr_common_vseq] io_div2_meas_ctrl_shadowed update_err alert timeout 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 104452513841110406902258011974204041539912485387742741445254878325371108181173 75
UVM_INFO @ 10106373438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch 1 test run
clkmgr_clk_handshake_intersig_mubi 25313330935623122161902194640570894385397485648896224836005366120993297717894 74
UVM_INFO @ 73649085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 87341108378142097413639600243322755188438480662317870713255182344467328723325 75
UVM_INFO @ 10355986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---