Simulation Results: csrng

 
04/07/2026 02:41:51 DVSim: v1.49.0 sha: 98a020b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.70 %
  • code
  • 96.20 %
  • assert
  • 96.94 %
  • func
  • 90.97 %
  • block
  • 98.53 %
  • line
  • 99.54 %
  • branch
  • 96.38 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
98.32%
V2S
98.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 25 25 100.00
csrng_smoke 4.000s 73.383us 25 25 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 32.000s 57.650us 1 1 100.00
csr_rw 5 5 100.00
csrng_csr_rw 32.000s 15.424us 5 5 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 116.000s 6394.292us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 33.000s 171.582us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
csrng_csr_mem_rw_with_rand_reset 32.000s 22.372us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
csrng_csr_rw 32.000s 15.424us 5 5 100.00
csrng_csr_aliasing 33.000s 171.582us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 28.000s 66.473us 200 200 100.00
alerts 500 500 100.00
csrng_alert 68.000s 5952.626us 500 500 100.00
err 500 500 100.00
csrng_err 32.000s 36.318us 500 500 100.00
cmds 3 25 12.00
csrng_cmds 80.000s 5464.506us 3 25 12.00
life cycle 3 25 12.00
csrng_cmds 80.000s 5464.506us 3 25 12.00
stress_all 25 25 100.00
csrng_stress_all 922.000s 40943.172us 25 25 100.00
intr_test 10 10 100.00
csrng_intr_test 24.000s 51.844us 10 10 100.00
alert_test 10 10 100.00
csrng_alert_test 32.000s 29.408us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
csrng_tl_errors 12.000s 730.488us 25 25 100.00
tl_d_illegal_access 25 25 100.00
csrng_tl_errors 12.000s 730.488us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
csrng_csr_hw_reset 32.000s 57.650us 1 1 100.00
csrng_csr_rw 32.000s 15.424us 5 5 100.00
csrng_csr_aliasing 33.000s 171.582us 1 1 100.00
csrng_same_csr_outstanding 16.000s 32.456us 5 5 100.00
tl_d_partial_access 12 12 100.00
csrng_csr_hw_reset 32.000s 57.650us 1 1 100.00
csrng_csr_rw 32.000s 15.424us 5 5 100.00
csrng_csr_aliasing 33.000s 171.582us 1 1 100.00
csrng_same_csr_outstanding 16.000s 32.456us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
csrng_sec_cm 12.000s 149.288us 5 5 100.00
csrng_tl_intg_err 23.000s 993.949us 25 25 100.00
sec_cm_config_regwen 14 30 46.67
csrng_regwen 24.000s 48.707us 9 25 36.00
csrng_csr_rw 32.000s 15.424us 5 5 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 68.000s 5952.626us 500 500 100.00
sec_cm_intersig_mubi 25 25 100.00
csrng_stress_all 922.000s 40943.172us 25 25 100.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 28.000s 66.473us 200 200 100.00
csrng_err 32.000s 36.318us 500 500 100.00
csrng_sec_cm 12.000s 149.288us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 28.000s 66.473us 200 200 100.00
csrng_err 32.000s 36.318us 500 500 100.00
csrng_sec_cm 12.000s 149.288us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 28.000s 66.473us 200 200 100.00
csrng_err 32.000s 36.318us 500 500 100.00
csrng_sec_cm 12.000s 149.288us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 28.000s 66.473us 200 200 100.00
csrng_err 32.000s 36.318us 500 500 100.00
csrng_sec_cm 12.000s 149.288us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 28.000s 66.473us 200 200 100.00
csrng_err 32.000s 36.318us 500 500 100.00
csrng_sec_cm 12.000s 149.288us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 68.000s 5952.626us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 28.000s 66.473us 200 200 100.00
csrng_err 32.000s 36.318us 500 500 100.00
sec_cm_constants_lc_gated 25 25 100.00
csrng_stress_all 922.000s 40943.172us 25 25 100.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 68.000s 5952.626us 500 500 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
csrng_tl_intg_err 23.000s 993.949us 25 25 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 28.000s 66.473us 200 200 100.00
csrng_err 32.000s 36.318us 500 500 100.00
csrng_sec_cm 12.000s 149.288us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 28.000s 66.473us 200 200 100.00
csrng_err 32.000s 36.318us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 28.000s 66.473us 200 200 100.00
csrng_err 32.000s 36.318us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 28.000s 66.473us 200 200 100.00
csrng_err 32.000s 36.318us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 28.000s 66.473us 200 200 100.00
csrng_err 32.000s 36.318us 500 500 100.00
csrng_sec_cm 12.000s 149.288us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 28.000s 66.473us 200 200 100.00
csrng_err 32.000s 36.318us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
csrng_stress_all_with_rand_reset 3601.000s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 22 test runs
csrng_cmds 29414979136314854523132871138691258686975581647002464850663946138185721855282 100
UVM_INFO @ 159078492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 75336136072338849338124271317330830845919345036528457985709493933729249395988 100
UVM_INFO @ 207336628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 77689314490746845080147463055143626452530777978329151151421316299945775333046 100
UVM_INFO @ 107533172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 25067840561221463675923252259099638657775396841045150405207629423203040437907 100
UVM_INFO @ 34060815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 106542056612177046221018310943063610259519702785081217179651080848107322212463 110
UVM_INFO @ 431372669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 88277855464142776281288712869799233546725629453276442757603647417314228510652 100
UVM_INFO @ 37382797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 103867569761248923550478687919260285867657613417633317012408415907882429968626 100
UVM_INFO @ 88709240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 79846436163820876319946497922213554542133223350712606772868990345303621659844 100
UVM_INFO @ 271580943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 62836245252189342830295818735152005885186285664901662840585073620707807148818 100
UVM_INFO @ 151409861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 106894434343111237979991112295650511856035367817514981244326540449257439607580 100
UVM_INFO @ 18130808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 48173217824139543521735363756852708948577841342040675759314190611460725883611 120
UVM_INFO @ 1080656198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 47320908308028098617322138489159084619531761323841004990515990681793558984712 100
UVM_INFO @ 114408516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 114810807065238270144403231467650053489366598891826795582018095954212167048747 100
UVM_INFO @ 163591236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 98465156811736241244324350134290991904408557453332367749592396337166484579468 100
UVM_INFO @ 22391517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 23982014862198621813656388079011273010811641262667709544307556127055650223855 100
UVM_INFO @ 115837511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 94511024524599985574636190977563472957726607436949798160127273484831970272569 100
UVM_INFO @ 10474461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 78057969484224354654996064304634629734746648680732098934042026895736632362991 100
UVM_INFO @ 80781051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 71360168318314912307047816226940739760707750441789449138800813992721921814632 110
UVM_INFO @ 140388677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 12331592184413573933959511137643999641860430757197344461680114885681145366496 100
UVM_INFO @ 915266816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 105132530633643209121557749149522452904517064326907260029426631536411360363175 100
UVM_INFO @ 100142888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 52130974988514566595646088773918762559564791411154280643745884618655972117502 100
UVM_INFO @ 174872820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 60985910660287563668481953723496291604071958676084111795516386605106028885162 100
UVM_INFO @ 25529381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 10 test runs
csrng_regwen 94588927494873019618667816374871604872543010502483315677636486489096378122305 99
UVM_INFO @ 48707125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 76356055677744810156113115564711116220530528543160607191844542510318894253559 99
UVM_INFO @ 2799432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 98097217355410787144355916437921307046906065022688582996386652795946248443789 99
UVM_INFO @ 2896262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 104169589830032709317438105421450968773689255548701798859164360466297523628239 99
UVM_INFO @ 2916196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 18009629506364844660593633596568059774228689831453214937016658981570734994876 99
UVM_INFO @ 4208081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 54295248816273184400533170584381223709509728073801117727350728908680534263335 99
UVM_INFO @ 3594501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 9254284319390157663365725837683289782899642213540991268923058269333698460269 99
UVM_INFO @ 16901685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 59168925862965597719428874866112520978941960311591227674829707976237098489048 99
UVM_INFO @ 1686161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 41564600383486204762371470800709558149210722574766080497213143997988752395604 99
UVM_INFO @ 3855602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 81094061357747194772529451470497717085831631092467591797162105666679039827671 99
UVM_INFO @ 4294172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 8 test runs
csrng_stress_all_with_rand_reset 46852696391064298165377908500806197673587309917568544466002118489037602785631 None
csrng_stress_all_with_rand_reset 17314794068512319702265334328219562365302520348945723045087372993673097757256 None
csrng_stress_all_with_rand_reset 60411280919038052998678673884394129398593213799475145639946352681409074311799 None
csrng_stress_all_with_rand_reset 35590983073633168553456383710240781621623719447661379645747734287570935292720 None
csrng_stress_all_with_rand_reset 85061222649832578133355348027771653027198865414796310249482365058514292054404 None
csrng_stress_all_with_rand_reset 99162808009137597932995667704896001102574044117505977517109890837877574545000 None
csrng_stress_all_with_rand_reset 46099674479680911582191405398320432367292228991801435100995336638921575322089 None
csrng_stress_all_with_rand_reset 45488883295831424554046023306702426590738710138069590886401689209339854992933 None
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 6 test runs
csrng_regwen 100428873365637315462911207269334736305646200756125309591366869109892333040254 99
UVM_INFO @ 12394567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 1984129292816454946290683843295995100667232421778336643834768158008707842185 99
UVM_INFO @ 1336327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 42299027182541683371965217510022114781183034585976219771225318499283172726454 99
UVM_INFO @ 1498899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 29461001641740866231040543940138231055097159929305553356254634186081303027413 99
UVM_INFO @ 7531181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 23941675607100860316009818060902663757986980250858312743479457345131338327821 99
UVM_INFO @ 12886093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 49603255675104424066007187470742552098427890461832988030071764235689762969910 99
UVM_INFO @ 6109417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 1 test run
csrng_stress_all_with_rand_reset 70738193291308093505530460181515748823547421457548953951312988953304000943005 145
UVM_INFO @ 11879109549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [csrng_common_vseq] Check failed (vseq_done) 1 test run
csrng_stress_all_with_rand_reset 25172819011555782505785711200436510382442793224560000816134113464646448645647 177
UVM_INFO @ 2473928214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---