Simulation Results: edn/edn0

 
04/07/2026 02:41:51 DVSim: v1.49.0 sha: 98a020b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.57 %
  • code
  • 95.35 %
  • assert
  • 98.70 %
  • func
  • 92.66 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 93.96 %
  • toggle
  • 97.07 %
  • FSM
  • 90.32 %
Validation stages
V1
100.00%
V2
99.01%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.340s 28.606us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.090s 26.777us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.130s 23.348us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.730s 160.512us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.440s 134.768us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.730s 62.693us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.130s 23.348us 5 5 100.00
edn_csr_aliasing 1.440s 134.768us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 3.260s 355.534us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 3.260s 355.534us 100 100 100.00
genbits 100 100 100.00
edn_genbits 3.260s 355.534us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.430s 20.075us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.670s 56.336us 200 200 100.00
errs 100 100 100.00
edn_err 1.510s 32.931us 100 100 100.00
disable 94 100 94.00
edn_disable 1.330s 14.247us 50 50 100.00
edn_disable_auto_req_mode 2.390s 500.000us 44 50 88.00
stress_all 30 30 100.00
edn_stress_all 9.490s 483.551us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.230s 39.604us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.160s 30.887us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.970s 170.982us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.970s 170.982us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.090s 26.777us 1 1 100.00
edn_csr_rw 1.130s 23.348us 5 5 100.00
edn_csr_aliasing 1.440s 134.768us 1 1 100.00
edn_same_csr_outstanding 1.720s 131.857us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.090s 26.777us 1 1 100.00
edn_csr_rw 1.130s 23.348us 5 5 100.00
edn_csr_aliasing 1.440s 134.768us 1 1 100.00
edn_same_csr_outstanding 1.720s 131.857us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 7.840s 4335.234us 5 5 100.00
edn_tl_intg_err 2.910s 348.954us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.090s 23.638us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.670s 56.336us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.840s 4335.234us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.840s 4335.234us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 7.840s 4335.234us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 7.840s 4335.234us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.670s 56.336us 200 200 100.00
edn_sec_cm 7.840s 4335.234us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.670s 56.336us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 2.910s 348.954us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 24 30 80.00
edn_stress_all_with_rand_reset 78.540s 46389.625us 24 30 80.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
edn_stress_all_with_rand_reset 20754835143366285152449007410094277957313240580363971931319871325561047984185 184
UVM_INFO @ 1082162712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 26053604830087477506399456771200647740896824193220801904292652683980953280658 235
UVM_INFO @ 429763709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 44861973490219841927755949335776561755700314063183207531173857345391247709870 219
UVM_INFO @ 2116648968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 96798143661049427170586923030408115936646317638842251208834160814394784604150 392
UVM_INFO @ 3096889193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 32225737901242806736409795189007275142405138059650865235099350464711909029806 181
UVM_INFO @ 1116474567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 3 test runs
edn_disable_auto_req_mode 95575848928698258362689863559711388591486504776863510712303798519567673838456 88
UVM_INFO @ 31077718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 30158047001292075123314735663041145629425392343692841909012641003252912647675 88
UVM_INFO @ 32582494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 1434377828220661587354208371428433449258764173773048688992257874343537473954 88
UVM_INFO @ 24535868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 3 test runs
edn_disable_auto_req_mode 95779825707914555164120169392704451588401477421725150924207810346009743140836 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 58852251767623297010479155850543357307319139735031988680634417105125753753728 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 88680139513578436935221568930532881953768362881868567902239264742299899489846 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit 1 test run
edn_stress_all_with_rand_reset 13133023881587569851674638783998672205990961544543943288593158161937851251346 266
/nightly/current_run/scratch/master/edn_edn0-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 2302260011 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup