Simulation Results

Simulation Results: edn/edn1

04/07/2026 02:41:51 DVSim: v1.49.0 sha: 98a020b json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
94.57 %

code
94.35 %

assert
97.14 %

func
92.23 %

line
98.48 %

branch
94.59 %

cond
94.54 %

toggle
88.70 %

FSM
95.45 %

Validation stages

V1		100.00%
V2		98.85%
V2S		100.00%
V3		90.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	edn_smoke	1.220s	27.050us	10	10	100.00
csr_hw_reset				1	1	100.00
	edn_csr_hw_reset	0.800s	19.198us	1	1	100.00
csr_rw				5	5	100.00
	edn_csr_rw	1.020s	21.957us	5	5	100.00
csr_bit_bash				1	1	100.00
	edn_csr_bit_bash	2.610s	159.096us	1	1	100.00
csr_aliasing				1	1	100.00
	edn_csr_aliasing	1.530s	79.878us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	edn_csr_mem_rw_with_rand_reset	1.880s	111.078us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	edn_csr_rw	1.020s	21.957us	5	5	100.00
	edn_csr_aliasing	1.530s	79.878us	1	1	100.00

600/607 passed

98.85 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
firmware				100	100	100.00
	edn_genbits	2.570s	68.407us	100	100	100.00
csrng_commands				100	100	100.00
	edn_genbits	2.570s	68.407us	100	100	100.00
genbits				100	100	100.00
	edn_genbits	2.570s	68.407us	100	100	100.00
interrupts				20	20	100.00
	edn_intr	1.180s	25.611us	20	20	100.00
alerts				200	200	100.00
	edn_alert	1.630s	31.758us	200	200	100.00
errs				100	100	100.00
	edn_err	1.730s	64.522us	100	100	100.00
disable				93	100	93.00
	edn_disable	1.130s	22.702us	50	50	100.00
	edn_disable_auto_req_mode	6.710s	500.000us	43	50	86.00
stress_all				30	30	100.00
	edn_stress_all	5.980s	340.002us	30	30	100.00
intr_test				10	10	100.00
	edn_intr_test	1.070s	17.812us	10	10	100.00
alert_test				10	10	100.00
	edn_alert_test	1.020s	67.365us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	edn_tl_errors	3.030s	511.052us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	edn_tl_errors	3.030s	511.052us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	edn_csr_hw_reset	0.800s	19.198us	1	1	100.00
	edn_csr_rw	1.020s	21.957us	5	5	100.00
	edn_csr_aliasing	1.530s	79.878us	1	1	100.00
	edn_same_csr_outstanding	1.200s	25.960us	5	5	100.00
tl_d_partial_access				12	12	100.00
	edn_csr_hw_reset	0.800s	19.198us	1	1	100.00
	edn_csr_rw	1.020s	21.957us	5	5	100.00
	edn_csr_aliasing	1.530s	79.878us	1	1	100.00
	edn_same_csr_outstanding	1.200s	25.960us	5	5	100.00

V2S

235/235 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	edn_sec_cm	3.450s	868.659us	5	5	100.00
	edn_tl_intg_err	2.030s	111.606us	25	25	100.00
sec_cm_config_regwen				5	5	100.00
	edn_regwen	1.120s	19.339us	5	5	100.00
sec_cm_config_mubi				200	200	100.00
	edn_alert	1.630s	31.758us	200	200	100.00
sec_cm_main_sm_fsm_sparse				5	5	100.00
	edn_sec_cm	3.450s	868.659us	5	5	100.00
sec_cm_ack_sm_fsm_sparse				5	5	100.00
	edn_sec_cm	3.450s	868.659us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	edn_sec_cm	3.450s	868.659us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	edn_sec_cm	3.450s	868.659us	5	5	100.00
sec_cm_main_sm_ctr_local_esc				205	205	100.00
	edn_alert	1.630s	31.758us	200	200	100.00
	edn_sec_cm	3.450s	868.659us	5	5	100.00
sec_cm_cs_rdata_bus_consistency				200	200	100.00
	edn_alert	1.630s	31.758us	200	200	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	edn_tl_intg_err	2.030s	111.606us	25	25	100.00

27/30 passed

90.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				27	30	90.00
	edn_stress_all_with_rand_reset	114.300s	16742.076us	27	30	90.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				6 test runs
	edn_disable_auto_req_mode	48988477818446355658722486007504076362702405789576507375446866861750064633112	89	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	1643144259077947802026728724182894525918543796409657118969505822986233552391	89	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	63520028174185538597702026651809302074798170635553928278854585224762112445784	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	88920354609407020706751052056071418438703617791296276725515817538694291788373	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	9946140107095414119550923106001847459143991757557259096756852472255180687834	89	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	49525382236232905230694826596818940935016877998784459692080872273616385777008	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	edn_stress_all_with_rand_reset	97323062514979011293467593400780587165801321011232115347629595687627049061450	188	UVM_INFO @ 1266411724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	29584096362341170203566276446913128552913983574190222735043047772250086901377	137	UVM_INFO @ 1165314918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.				1 test run
	edn_disable_auto_req_mode	46160361137508167951894090155143378049883363165725521342618548639593399988169	88	UVM_INFO @ 122167894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred!				1 test run
	edn_stress_all_with_rand_reset	78501640624920892156110307601942568519045186976740130366277871460839798357236	357	UVM_INFO @ 16742075910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---