Simulation Results

Simulation Results: flash_ctrl

04/07/2026 02:41:51 DVSim: v1.49.0 sha: 98a020b json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
97.05 %

code
95.91 %

assert
96.94 %

func
98.30 %

line
96.10 %

branch
97.42 %

cond
94.87 %

toggle
98.66 %

FSM
92.52 %

Validation stages

V1		100.00%
V2		98.40%
V2S		98.74%
V3		100.00%
unmapped		100.00%

70/70 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	flash_ctrl_smoke	211.180s	74.562us	50	50	100.00
smoke_hw				5	5	100.00
	flash_ctrl_smoke_hw	26.660s	57.274us	5	5	100.00
csr_hw_reset				1	1	100.00
	flash_ctrl_csr_hw_reset	11.540s	108.860us	1	1	100.00
csr_rw				5	5	100.00
	flash_ctrl_csr_rw	18.800s	78.728us	5	5	100.00
csr_bit_bash				1	1	100.00
	flash_ctrl_csr_bit_bash	107.290s	66432.229us	1	1	100.00
csr_aliasing				1	1	100.00
	flash_ctrl_csr_aliasing	40.460s	1680.878us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	flash_ctrl_csr_mem_rw_with_rand_reset	18.290s	182.495us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	flash_ctrl_csr_rw	18.800s	78.728us	5	5	100.00
	flash_ctrl_csr_aliasing	40.460s	1680.878us	1	1	100.00
mem_walk				1	1	100.00
	flash_ctrl_mem_walk	12.280s	55.259us	1	1	100.00
mem_partial_access				1	1	100.00
	flash_ctrl_mem_partial_access	12.770s	32.785us	1	1	100.00

920/935 passed

98.40 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sw_op				5	5	100.00
	flash_ctrl_sw_op	24.450s	54.519us	5	5	100.00
host_read_direct				5	5	100.00
	flash_ctrl_host_dir_rd	40.950s	232.460us	5	5	100.00
rma_hw_if				42	43	97.67
	flash_ctrl_hw_rma	1383.610s	103414.050us	3	3	100.00
	flash_ctrl_hw_rma_reset	738.820s	80144.452us	20	20	100.00
	flash_ctrl_lcmgr_intg	15.180s	199.686us	19	20	95.00
host_controller_arb				5	5	100.00
	flash_ctrl_host_ctrl_arb	1781.410s	255591.004us	5	5	100.00
erase_suspend				5	5	100.00
	flash_ctrl_erase_suspend	260.040s	20867.805us	5	5	100.00
program_reset				29	30	96.67
	flash_ctrl_prog_reset	3604.012s	0.000us	29	30	96.67
full_memory_access				5	5	100.00
	flash_ctrl_full_mem_access	2815.380s	570732.541us	5	5	100.00
rd_buff_eviction				5	5	100.00
	flash_ctrl_rd_buff_evict	86.710s	759.952us	5	5	100.00
rd_buff_eviction_w_ecc				100	105	95.24
	flash_ctrl_rw_evict	34.500s	43.935us	37	40	92.50
	flash_ctrl_rw_evict_all_en	34.490s	28.802us	38	40	95.00
	flash_ctrl_re_evict	37.760s	72.151us	25	25	100.00
host_arb				20	20	100.00
	flash_ctrl_phy_arb	217.130s	363.968us	20	20	100.00
host_interleave				20	20	100.00
	flash_ctrl_phy_arb	217.130s	363.968us	20	20	100.00
memory_protection				20	20	100.00
	flash_ctrl_mp_regions	679.530s	46427.070us	20	20	100.00
fetch_code				10	10	100.00
	flash_ctrl_fetch_code	30.640s	3983.968us	10	10	100.00
all_partitions				20	20	100.00
	flash_ctrl_rand_ops	865.070s	1531.664us	20	20	100.00
error_mp				10	10	100.00
	flash_ctrl_error_mp	678.720s	6320.805us	10	10	100.00
error_prog_win				10	10	100.00
	flash_ctrl_error_prog_win	505.950s	2496.911us	10	10	100.00
error_prog_type				5	5	100.00
	flash_ctrl_error_prog_type	1909.890s	879.207us	5	5	100.00
error_read_seed				20	20	100.00
	flash_ctrl_hw_read_seed_err	14.790s	79.127us	20	20	100.00
read_write_overflow				5	5	100.00
	flash_ctrl_oversize_error	152.280s	6845.297us	5	5	100.00
flash_ctrl_disable				50	50	100.00
	flash_ctrl_disable	24.340s	34.262us	50	50	100.00
flash_ctrl_connect				80	80	100.00
	flash_ctrl_connect	18.200s	17.283us	80	80	100.00
stress_all				5	5	100.00
	flash_ctrl_stress_all	1219.640s	1236.445us	5	5	100.00
secret_partition				130	130	100.00
	flash_ctrl_hw_sec_otp	180.650s	32924.102us	50	50	100.00
	flash_ctrl_otp_reset	121.430s	78.076us	80	80	100.00
isolation_partition				3	3	100.00
	flash_ctrl_hw_rma	1383.610s	103414.050us	3	3	100.00
interrupts				95	100	95.00
	flash_ctrl_intr_rd	200.530s	3333.991us	37	40	92.50
	flash_ctrl_intr_wr	3604.010s	0.000us	9	10	90.00
	flash_ctrl_intr_rd_slow_flash	332.700s	24208.285us	40	40	100.00
	flash_ctrl_intr_wr_slow_flash	3604.011s	0.000us	9	10	90.00
invalid_op				20	20	100.00
	flash_ctrl_invalid_op	66.920s	972.511us	20	20	100.00
mid_op_rst				5	5	100.00
	flash_ctrl_mid_op_rst	70.450s	1019.340us	5	5	100.00
double_bit_err				35	35	100.00
	flash_ctrl_read_word_sweep_derr	20.810s	30.983us	5	5	100.00
	flash_ctrl_ro_derr	125.260s	1880.890us	10	10	100.00
	flash_ctrl_rw_derr	191.150s	8405.181us	10	10	100.00
	flash_ctrl_derr_detect	135.200s	1337.288us	5	5	100.00
	flash_ctrl_integrity	425.530s	10351.998us	5	5	100.00
single_bit_err				25	25	100.00
	flash_ctrl_read_word_sweep_serr	24.720s	30.970us	5	5	100.00
	flash_ctrl_ro_serr	111.650s	2878.105us	10	10	100.00
	flash_ctrl_rw_serr	158.270s	2258.311us	10	10	100.00
singlebit_err_counter				5	5	100.00
	flash_ctrl_serr_counter	73.730s	2080.107us	5	5	100.00
singlebit_err_address				5	5	100.00
	flash_ctrl_serr_address	82.910s	1234.329us	5	5	100.00
scramble				60	62	96.77
	flash_ctrl_wo	757.430s	200000.000us	19	20	95.00
	flash_ctrl_write_word_sweep	14.250s	44.494us	1	1	100.00
	flash_ctrl_read_word_sweep	6.820s	55.358us	1	1	100.00
	flash_ctrl_ro	109.680s	8905.333us	20	20	100.00
	flash_ctrl_rw	3604.011s	0.000us	19	20	95.00
filesystem_support				4	5	80.00
	flash_ctrl_fs_sup	35.450s	425.374us	4	5	80.00
rma_write_process_error				23	23	100.00
	flash_ctrl_rma_err	701.340s	236772.168us	3	3	100.00
	flash_ctrl_hw_prog_rma_wipe_err	131.700s	10035.572us	20	20	100.00
alert_test				10	10	100.00
	flash_ctrl_alert_test	14.760s	139.786us	10	10	100.00
intr_test				10	10	100.00
	flash_ctrl_intr_test	14.120s	95.748us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	flash_ctrl_tl_errors	21.570s	328.826us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	flash_ctrl_tl_errors	21.570s	328.826us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	flash_ctrl_csr_hw_reset	11.540s	108.860us	1	1	100.00
	flash_ctrl_csr_rw	18.800s	78.728us	5	5	100.00
	flash_ctrl_csr_aliasing	40.460s	1680.878us	1	1	100.00
	flash_ctrl_same_csr_outstanding	23.370s	437.965us	5	5	100.00
tl_d_partial_access				12	12	100.00
	flash_ctrl_csr_hw_reset	11.540s	108.860us	1	1	100.00
	flash_ctrl_csr_rw	18.800s	78.728us	5	5	100.00
	flash_ctrl_csr_aliasing	40.460s	1680.878us	1	1	100.00
	flash_ctrl_same_csr_outstanding	23.370s	437.965us	5	5	100.00

V2S

469/475 passed

98.74 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	83.890s	165.429us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	flash_ctrl_shadow_reg_errors	83.890s	165.429us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	83.890s	165.429us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	flash_ctrl_shadow_reg_errors	83.890s	165.429us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	flash_ctrl_shadow_reg_errors_with_csr_rw	65.850s	397.433us	20	20	100.00
tl_intg_err				29	30	96.67
	flash_ctrl_sec_cm	2361.040s	3340.150us	5	5	100.00
	flash_ctrl_tl_intg_err	586.190s	6923.534us	24	25	96.00
sec_cm_reg_bus_integrity				24	25	96.00
	flash_ctrl_tl_intg_err	586.190s	6923.534us	24	25	96.00
sec_cm_host_bus_integrity				24	25	96.00
	flash_ctrl_tl_intg_err	586.190s	6923.534us	24	25	96.00
sec_cm_mem_bus_integrity				6	6	100.00
	flash_ctrl_rd_intg	34.240s	73.901us	3	3	100.00
	flash_ctrl_wr_intg	15.230s	48.818us	3	3	100.00
sec_cm_scramble_key_sideload				50	50	100.00
	flash_ctrl_smoke	211.180s	74.562us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				260	260	100.00
	flash_ctrl_otp_reset	121.430s	78.076us	80	80	100.00
	flash_ctrl_disable	24.340s	34.262us	50	50	100.00
	flash_ctrl_sec_info_access	82.770s	9755.571us	50	50	100.00
	flash_ctrl_connect	18.200s	17.283us	80	80	100.00
sec_cm_ctrl_config_regwen				5	5	100.00
	flash_ctrl_config_regwen	14.930s	39.618us	5	5	100.00
sec_cm_data_regions_config_regwen				5	5	100.00
	flash_ctrl_csr_rw	18.800s	78.728us	5	5	100.00
sec_cm_data_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	83.890s	165.429us	20	20	100.00
sec_cm_info_regions_config_regwen				5	5	100.00
	flash_ctrl_csr_rw	18.800s	78.728us	5	5	100.00
sec_cm_info_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	83.890s	165.429us	20	20	100.00
sec_cm_bank_config_regwen				5	5	100.00
	flash_ctrl_csr_rw	18.800s	78.728us	5	5	100.00
sec_cm_bank_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	83.890s	165.429us	20	20	100.00
sec_cm_mem_ctrl_global_esc				50	50	100.00
	flash_ctrl_disable	24.340s	34.262us	50	50	100.00
sec_cm_mem_ctrl_local_esc				6	6	100.00
	flash_ctrl_rd_intg	34.240s	73.901us	3	3	100.00
	flash_ctrl_access_after_disable	12.680s	28.018us	3	3	100.00
sec_cm_mem_addr_infection				3	3	100.00
	flash_ctrl_host_addr_infection	26.420s	196.952us	3	3	100.00
sec_cm_mem_disable_config_mubi				50	50	100.00
	flash_ctrl_disable	24.340s	34.262us	50	50	100.00
sec_cm_exec_config_redun				10	10	100.00
	flash_ctrl_fetch_code	30.640s	3983.968us	10	10	100.00
sec_cm_mem_scramble				19	20	95.00
	flash_ctrl_rw	3604.011s	0.000us	19	20	95.00
sec_cm_mem_integrity				25	25	100.00
	flash_ctrl_rw_serr	158.270s	2258.311us	10	10	100.00
	flash_ctrl_rw_derr	191.150s	8405.181us	10	10	100.00
	flash_ctrl_integrity	425.530s	10351.998us	5	5	100.00
sec_cm_rma_entry_mem_sec_wipe				3	3	100.00
	flash_ctrl_hw_rma	1383.610s	103414.050us	3	3	100.00
sec_cm_ctrl_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2361.040s	3340.150us	5	5	100.00
sec_cm_phy_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2361.040s	3340.150us	5	5	100.00
sec_cm_phy_prog_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2361.040s	3340.150us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2361.040s	3340.150us	5	5	100.00
sec_cm_phy_arbiter_ctrl_redun				5	5	100.00
	flash_ctrl_phy_arb_redun	15.910s	924.549us	5	5	100.00
sec_cm_phy_host_grant_ctrl_consistency				2	5	40.00
	flash_ctrl_phy_host_grant_err	14.580s	11.902us	2	5	40.00
sec_cm_phy_ack_ctrl_consistency				4	5	80.00
	flash_ctrl_phy_ack_consistency	10.380s	81.727us	4	5	80.00
sec_cm_fifo_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2361.040s	3340.150us	5	5	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2361.040s	3340.150us	5	5	100.00
sec_cm_prog_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2361.040s	3340.150us	5	5	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
asymmetric_read_path				1	1	100.00
	flash_ctrl_rd_ooo	24.820s	42.454us	1	1	100.00

unmapped

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				3	3	100.00
	flash_ctrl_basic_rw	524.470s	889.336us	3	3	100.00

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				4 test runs
	flash_ctrl_intr_wr_slow_flash	45956067180811658731133614673690359022775103360477493546867703964178702123910	None
	flash_ctrl_intr_wr	66204724304376436552770553540204436482843931601954815600235447880939217738747	None
	flash_ctrl_rw	57089407774940546589517020394750701870512074519164249749143603338748013241067	None
	flash_ctrl_prog_reset	50984486257371526330533699490077308781985404211444120933729834442409975109114	None
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'				3 test runs
	flash_ctrl_phy_host_grant_err	97650093488279133570879036409851752896228349646144728168444415569633169521330	125	UVM_ERROR @ 50411.2 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 50411.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_phy_host_grant_err	47755251288113259638980177710080798109408224591653173625379041111886046534746	125	UVM_ERROR @ 33228.0 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 33228.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_phy_host_grant_err	102620510123948658480327747164016282626556810415262360684998258487352157881645	125	UVM_ERROR @ 11901.6 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 11901.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.op_status.err reset value:				3 test runs
	flash_ctrl_rw_evict_all_en	78105862191790530009071409716418153215995685272486523678586088075171577391059	108	UVM_INFO @ 55765.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict	21844020991295578100053713878798832009894820123573128179212800108672499458685	108	UVM_INFO @ 33259.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict_all_en	68217310520675654513180476584602737965567230787585569194727252747896173244440	108	UVM_INFO @ 61623.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value:				2 test runs
	flash_ctrl_rw_evict	41460199455730664567918822767197961703878775905752693704846603438922313630146	108	UVM_INFO @ 121877.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict	82697723702807704118577308987188592050084453105313120422692717936580919780293	108	UVM_INFO @ 14206.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp ba811_27acb4c9:ffffffff_ffffffff mismatch!!				1 test run
	flash_ctrl_intr_rd	115387427180040983793472303939804683742912057423829356531113834196217042194011	108	UVM_INFO @ 2481718.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act () != exp ()				1 test run
	flash_ctrl_phy_ack_consistency	54163014592275540731887080675441006875585353729454710124644035750281291039116	109	UVM_INFO @ 5668.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert fatal_err triggered unexpectedly				1 test run
	flash_ctrl_fs_sup	765510781990004955507410526879739181805496546642884642663947703021164998793	108	UVM_INFO @ 341371.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (alert_receiver_driver.sv:262) driver [driver] m_transaction_tasks nonempty after reset: '{:}				1 test run
	flash_ctrl_tl_intg_err	81223397426910926659750743889434763463215297089446016726188611345262967366894	350	UVM_INFO @ 246071.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value:				1 test run
	flash_ctrl_lcmgr_intg	8726193781667462330015627162531817630147314394249453737057909579172873439719	111	UVM_INFO @ 47611.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp b70d_dbc03c49:ffffffff_ffffffff mismatch!!				1 test run
	flash_ctrl_intr_rd	77785356118992216784196833481721565049079424820349748033027149602508273310291	108	UVM_INFO @ 1409130.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue				1 test run
	flash_ctrl_wo	60142732668710054167759638352692224238764073228862185833866577604738698655007	108	UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp ad1cccff_367661bb:ffffffff_ffffffff mismatch!!				1 test run
	flash_ctrl_intr_rd	36103904224985984803892531810403157956576566523762277248648840988157737227526	108	UVM_INFO @ 17703556.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---