Simulation Results: hmac

 
04/07/2026 02:41:51 DVSim: v1.49.0 sha: 98a020b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.65 %
  • code
  • 98.61 %
  • assert
  • 97.60 %
  • func
  • 99.73 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.57 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 12.960s 463.276us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.800s 21.933us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.130s 25.543us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.990s 1328.632us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.070s 56.082us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 2.430s 83.811us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.130s 25.543us 5 5 100.00
hmac_csr_aliasing 3.070s 56.082us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 84.210s 83714.615us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 90.150s 2194.876us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 257.230s 42659.760us 30 30 100.00
hmac_test_sha384_vectors 550.490s 54967.182us 75 75 100.00
hmac_test_sha512_vectors 549.630s 52589.569us 75 75 100.00
hmac_test_hmac256_vectors 12.940s 484.896us 50 50 100.00
hmac_test_hmac384_vectors 17.830s 694.294us 60 60 100.00
hmac_test_hmac512_vectors 18.440s 520.885us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 43.610s 1213.246us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1063.370s 9066.101us 10 10 100.00
error 10 10 100.00
hmac_error 80.910s 17227.803us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 127.480s 26090.998us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 12.960s 463.276us 10 10 100.00
hmac_long_msg 84.210s 83714.615us 10 10 100.00
hmac_back_pressure 90.150s 2194.876us 25 25 100.00
hmac_datapath_stress 1063.370s 9066.101us 10 10 100.00
hmac_burst_wr 43.610s 1213.246us 50 50 100.00
hmac_stress_all 2775.490s 141744.937us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 12.960s 463.276us 10 10 100.00
hmac_long_msg 84.210s 83714.615us 10 10 100.00
hmac_back_pressure 90.150s 2194.876us 25 25 100.00
hmac_datapath_stress 1063.370s 9066.101us 10 10 100.00
hmac_wipe_secret 127.480s 26090.998us 10 10 100.00
hmac_test_sha256_vectors 257.230s 42659.760us 30 30 100.00
hmac_test_sha384_vectors 550.490s 54967.182us 75 75 100.00
hmac_test_sha512_vectors 549.630s 52589.569us 75 75 100.00
hmac_test_hmac256_vectors 12.940s 484.896us 50 50 100.00
hmac_test_hmac384_vectors 17.830s 694.294us 60 60 100.00
hmac_test_hmac512_vectors 18.440s 520.885us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 12.960s 463.276us 10 10 100.00
hmac_long_msg 84.210s 83714.615us 10 10 100.00
hmac_back_pressure 90.150s 2194.876us 25 25 100.00
hmac_datapath_stress 1063.370s 9066.101us 10 10 100.00
hmac_burst_wr 43.610s 1213.246us 50 50 100.00
hmac_error 80.910s 17227.803us 10 10 100.00
hmac_wipe_secret 127.480s 26090.998us 10 10 100.00
hmac_test_sha256_vectors 257.230s 42659.760us 30 30 100.00
hmac_test_sha384_vectors 550.490s 54967.182us 75 75 100.00
hmac_test_sha512_vectors 549.630s 52589.569us 75 75 100.00
hmac_test_hmac256_vectors 12.940s 484.896us 50 50 100.00
hmac_test_hmac384_vectors 17.830s 694.294us 60 60 100.00
hmac_test_hmac512_vectors 18.440s 520.885us 75 75 100.00
hmac_stress_all 2775.490s 141744.937us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2775.490s 141744.937us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 0.930s 15.829us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 0.960s 12.242us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 4.430s 227.651us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 4.430s 227.651us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 0.800s 21.933us 1 1 100.00
hmac_csr_rw 1.130s 25.543us 5 5 100.00
hmac_csr_aliasing 3.070s 56.082us 1 1 100.00
hmac_same_csr_outstanding 2.930s 307.354us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 0.800s 21.933us 1 1 100.00
hmac_csr_rw 1.130s 25.543us 5 5 100.00
hmac_csr_aliasing 3.070s 56.082us 1 1 100.00
hmac_same_csr_outstanding 2.930s 307.354us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 1.240s 213.063us 5 5 100.00
hmac_tl_intg_err 4.810s 1086.969us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 4.810s 1086.969us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 12.960s 463.276us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 6.150s 108.980us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 392.460s 8967.059us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.940s 52.755us 1 1 100.00