Simulation Results: keymgr

 
04/07/2026 02:41:51 DVSim: v1.49.0 sha: 98a020b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.88 %
  • code
  • 98.80 %
  • assert
  • 97.72 %
  • func
  • 91.11 %
  • line
  • 99.20 %
  • branch
  • 99.00 %
  • cond
  • 98.12 %
  • toggle
  • 97.70 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.53%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 30 30 100.00
keymgr_smoke 16.570s 2619.729us 30 30 100.00
random 30 30 100.00
keymgr_random 56.940s 10351.473us 30 30 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.260s 75.817us 1 1 100.00
csr_rw 5 5 100.00
keymgr_csr_rw 1.270s 38.821us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 17.420s 760.162us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 6.250s 126.183us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_csr_mem_rw_with_rand_reset 1.950s 221.368us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_csr_rw 1.270s 38.821us 5 5 100.00
keymgr_csr_aliasing 6.250s 126.183us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 75.680s 8963.010us 50 50 100.00
sideload 80 80 100.00
keymgr_sideload 47.030s 5740.723us 20 20 100.00
keymgr_sideload_kmac 29.520s 5134.053us 20 20 100.00
keymgr_sideload_aes 18.860s 782.817us 20 20 100.00
keymgr_sideload_otbn 36.470s 7178.635us 20 20 100.00
direct_to_disabled_state 30 30 100.00
keymgr_direct_to_disabled 24.740s 18739.391us 30 30 100.00
lc_disable 50 50 100.00
keymgr_lc_disable 9.880s 501.752us 50 50 100.00
kmac_error_response 20 20 100.00
keymgr_kmac_rsp_err 9.220s 815.639us 20 20 100.00
invalid_sw_input 20 20 100.00
keymgr_sw_invalid_input 38.800s 17680.174us 20 20 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 24.010s 1501.633us 50 50 100.00
sync_async_fault_cross 20 20 100.00
keymgr_sync_async_fault_cross 21.310s 5198.687us 20 20 100.00
stress_all 48 50 96.00
keymgr_stress_all 343.710s 94646.650us 48 50 96.00
intr_test 10 10 100.00
keymgr_intr_test 1.200s 65.012us 10 10 100.00
alert_test 10 10 100.00
keymgr_alert_test 1.250s 24.736us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_tl_errors 4.880s 139.342us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_tl_errors 4.880s 139.342us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_csr_hw_reset 1.260s 75.817us 1 1 100.00
keymgr_csr_rw 1.270s 38.821us 5 5 100.00
keymgr_csr_aliasing 6.250s 126.183us 1 1 100.00
keymgr_same_csr_outstanding 4.320s 119.847us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_csr_hw_reset 1.260s 75.817us 1 1 100.00
keymgr_csr_rw 1.270s 38.821us 5 5 100.00
keymgr_csr_aliasing 6.250s 126.183us 1 1 100.00
keymgr_same_csr_outstanding 4.320s 119.847us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 18.850s 981.435us 5 5 100.00
tl_intg_err 30 30 100.00
keymgr_sec_cm 18.850s 981.435us 5 5 100.00
keymgr_tl_intg_err 10.380s 537.406us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 5.000s 363.142us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 5.000s 363.142us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 5.000s 363.142us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 5.000s 363.142us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 15.560s 2155.392us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 18.850s 981.435us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 18.850s 981.435us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
keymgr_tl_intg_err 10.380s 537.406us 25 25 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 5.000s 363.142us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 75.680s 8963.010us 50 50 100.00
sec_cm_reseed_config_regwen 35 35 100.00
keymgr_random 56.940s 10351.473us 30 30 100.00
keymgr_csr_rw 1.270s 38.821us 5 5 100.00
sec_cm_sw_binding_config_regwen 35 35 100.00
keymgr_random 56.940s 10351.473us 30 30 100.00
keymgr_csr_rw 1.270s 38.821us 5 5 100.00
sec_cm_max_key_ver_config_regwen 35 35 100.00
keymgr_random 56.940s 10351.473us 30 30 100.00
keymgr_csr_rw 1.270s 38.821us 5 5 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
keymgr_lc_disable 9.880s 501.752us 50 50 100.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 24.010s 1501.633us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 24.010s 1501.633us 50 50 100.00
sec_cm_hw_key_sw_noaccess 30 30 100.00
keymgr_random 56.940s 10351.473us 30 30 100.00
sec_cm_output_keys_ctrl_redun 20 20 100.00
keymgr_sideload_protect 20.840s 1170.662us 20 20 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 18.850s 981.435us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 18.850s 981.435us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 18.850s 981.435us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 15.410s 2755.779us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 50 50 100.00
keymgr_lc_disable 9.880s 501.752us 50 50 100.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 18.850s 981.435us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 18.850s 981.435us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 18.850s 981.435us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 15.410s 2755.779us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 15.410s 2755.779us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 18.850s 981.435us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 15.410s 2755.779us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 18.850s 981.435us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 15.410s 2755.779us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 20 50.00
keymgr_stress_all_with_rand_reset 22.290s 2077.213us 10 20 50.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 9 test runs
keymgr_stress_all_with_rand_reset 18198525217248270678087670370052153468266989167571634485712940201522227626043 241
UVM_INFO @ 920079445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 11266803451461984733707155538404138444068901201780757017089914276894474808247 97
UVM_INFO @ 109225685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 24443729431008257592031940321469956280610346881027905549888619418119928463706 285
UVM_INFO @ 129041243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 100148490602954320645775339042102143208432258359242442245818098046531784052824 765
UVM_INFO @ 3000687002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 87820887715552559115052915411791435449136592318951678013985420458906154985274 126
UVM_INFO @ 422174665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 85940167635963143503339749952527201579827120640872270196765626708132136910457 348
UVM_INFO @ 170699913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 4754117092650561009863354909609258851626896469694897614751175378912238992552 137
UVM_INFO @ 518749746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 19734181780435164801951609558738242546074389545509651252878293520140690364746 256
UVM_INFO @ 593768061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 23224554253880843895880872301769755284758313318416038340576473004767841864608 384
UVM_INFO @ 104712057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* 1 test run
keymgr_stress_all_with_rand_reset 55228293610787659549202448830465469739124411201757008393516905779471075206132 264
UVM_INFO @ 133017534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*]) 1 test run
keymgr_stress_all 85708905214132276412906061051998836928724074701254536092294378407180193451055 882
UVM_INFO @ 210374480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_* 1 test run
keymgr_stress_all 107307801973726705803098583297037164759323215233013608955231270457688684872694 501
UVM_INFO @ 661031324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---