Simulation Results: lc_ctrl/volatile_unlock_disabled

 
04/07/2026 02:41:51 DVSim: v1.49.0 sha: 98a020b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.40 %
  • code
  • 86.02 %
  • assert
  • 94.55 %
  • func
  • 96.62 %
  • line
  • 97.28 %
  • branch
  • 93.85 %
  • cond
  • 81.55 %
  • toggle
  • 88.25 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
99.77%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 6.990s 156.929us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.280s 61.167us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.280s 25.317us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.690s 108.939us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.420s 16.948us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.580s 40.296us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.280s 25.317us 5 5 100.00
lc_ctrl_csr_aliasing 1.420s 16.948us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 9.720s 583.844us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 11.770s 722.199us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.360s 13.781us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 6.590s 849.698us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 14.140s 364.889us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 20.030s 3531.856us 20 20 100.00
security_escalation 139 140 99.29
lc_ctrl_state_failure 14.140s 364.889us 20 20 100.00
lc_ctrl_prog_failure 6.590s 849.698us 20 20 100.00
lc_ctrl_errors 20.030s 3531.856us 20 20 100.00
lc_ctrl_security_escalation 11.720s 2205.934us 20 20 100.00
lc_ctrl_jtag_state_failure 59.500s 2538.062us 20 20 100.00
lc_ctrl_jtag_prog_failure 14.960s 1023.977us 20 20 100.00
lc_ctrl_jtag_errors 59.460s 2243.115us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 7.920s 447.619us 20 20 100.00
lc_ctrl_jtag_state_post_trans 29.610s 994.999us 20 20 100.00
lc_ctrl_jtag_prog_failure 14.960s 1023.977us 20 20 100.00
lc_ctrl_jtag_errors 59.460s 2243.115us 19 20 95.00
lc_ctrl_jtag_access 17.770s 1515.689us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 29.450s 17130.279us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.440s 455.716us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.320s 539.152us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 16.060s 804.659us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 28.480s 1309.390us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.190s 250.159us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 6.320s 556.485us 10 10 100.00
lc_ctrl_jtag_alert_test 2.810s 500.772us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 22.710s 5054.527us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.250s 17.294us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 331.920s 13708.070us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.490s 21.600us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 5.210s 126.618us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 5.210s 126.618us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.280s 61.167us 1 1 100.00
lc_ctrl_csr_rw 1.280s 25.317us 5 5 100.00
lc_ctrl_csr_aliasing 1.420s 16.948us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.910s 43.105us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.280s 61.167us 1 1 100.00
lc_ctrl_csr_rw 1.280s 25.317us 5 5 100.00
lc_ctrl_csr_aliasing 1.420s 16.948us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.910s 43.105us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 11.710s 223.247us 5 5 100.00
lc_ctrl_tl_intg_err 4.660s 682.749us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.660s 682.749us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 11.770s 722.199us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 14.140s 364.889us 20 20 100.00
lc_ctrl_sec_cm 11.710s 223.247us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 14.140s 364.889us 20 20 100.00
lc_ctrl_sec_cm 11.710s 223.247us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 14.140s 364.889us 20 20 100.00
lc_ctrl_sec_cm 11.710s 223.247us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 14.140s 364.889us 20 20 100.00
lc_ctrl_sec_cm 11.710s 223.247us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 14.140s 364.889us 20 20 100.00
lc_ctrl_sec_cm 11.710s 223.247us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 14.140s 364.889us 20 20 100.00
lc_ctrl_sec_cm 11.710s 223.247us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 14.140s 364.889us 20 20 100.00
lc_ctrl_sec_cm 11.710s 223.247us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 14.140s 364.889us 20 20 100.00
lc_ctrl_sec_cm 11.710s 223.247us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 11.720s 2205.934us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 9.720s 583.844us 20 20 100.00
lc_ctrl_jtag_state_post_trans 29.610s 994.999us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 14.040s 5022.777us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 14.040s 5022.777us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 19.610s 5413.291us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 14.360s 1879.819us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 14.360s 1879.819us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
lc_ctrl_stress_all_with_rand_reset 149.940s 5375.887us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
lc_ctrl_stress_all_with_rand_reset 60798887773627322164454234207790969199665366617517889664645077393045782071279 3283
UVM_INFO @ 1629695021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 17917338517628578105900035065857771586779431852698309139745442218947740686386 8264
UVM_INFO @ 10419098789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 37642250373440978499930716405419874201547572448867019606314846440009347423127 1415
UVM_INFO @ 7593730921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 35833408129643960258272849621956239725025414265080404477419498790323873656277 1243
UVM_INFO @ 3790231563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 108057295034001955531749527943610042754859298774228059412012618135274509533004 1749
UVM_INFO @ 1243691966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 13748695671502079057235191516657215274374832115796243200642412100272538340208 213
UVM_INFO @ 1333745580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_jtag_errors 28538114573313357596986871930495887538460349730693339690151043022058226067796 2695
UVM_INFO @ 9297286428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---