Simulation Results: lc_ctrl/volatile_unlock_enabled

 
04/07/2026 02:41:51 DVSim: v1.49.0 sha: 98a020b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.48 %
  • code
  • 86.08 %
  • assert
  • 94.55 %
  • func
  • 96.80 %
  • line
  • 97.26 %
  • branch
  • 93.95 %
  • cond
  • 81.76 %
  • toggle
  • 88.25 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
99.53%
V2S
100.00%
V3
20.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 4.190s 1662.325us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.210s 156.200us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.430s 16.807us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.910s 180.072us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.270s 74.767us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.740s 41.497us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.430s 16.807us 5 5 100.00
lc_ctrl_csr_aliasing 1.270s 74.767us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 10.580s 96.303us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 14.550s 588.454us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.260s 13.787us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.810s 484.619us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 13.080s 1360.246us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 14.210s 689.685us 19 20 95.00
security_escalation 139 140 99.29
lc_ctrl_state_failure 13.080s 1360.246us 20 20 100.00
lc_ctrl_prog_failure 3.810s 484.619us 20 20 100.00
lc_ctrl_errors 14.210s 689.685us 19 20 95.00
lc_ctrl_security_escalation 12.490s 387.656us 20 20 100.00
lc_ctrl_jtag_state_failure 47.920s 9873.507us 20 20 100.00
lc_ctrl_jtag_prog_failure 12.150s 3162.961us 20 20 100.00
lc_ctrl_jtag_errors 45.780s 1923.549us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 12.750s 3121.738us 20 20 100.00
lc_ctrl_jtag_state_post_trans 26.720s 1684.066us 20 20 100.00
lc_ctrl_jtag_prog_failure 12.150s 3162.961us 20 20 100.00
lc_ctrl_jtag_errors 45.780s 1923.549us 20 20 100.00
lc_ctrl_jtag_access 16.000s 1011.931us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 20.410s 3618.212us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.220s 570.716us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.760s 74.170us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 20.170s 808.237us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 11.020s 1051.886us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.760s 21.901us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.700s 1050.788us 10 10 100.00
lc_ctrl_jtag_alert_test 2.330s 76.258us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 15.100s 13163.610us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.420s 23.585us 10 10 100.00
stress_all 9 10 90.00
lc_ctrl_stress_all 300.050s 165239.630us 9 10 90.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.650s 25.233us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.540s 626.809us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.540s 626.809us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.210s 156.200us 1 1 100.00
lc_ctrl_csr_rw 1.430s 16.807us 5 5 100.00
lc_ctrl_csr_aliasing 1.270s 74.767us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.400s 88.266us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.210s 156.200us 1 1 100.00
lc_ctrl_csr_rw 1.430s 16.807us 5 5 100.00
lc_ctrl_csr_aliasing 1.270s 74.767us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.400s 88.266us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 8.750s 486.397us 5 5 100.00
lc_ctrl_tl_intg_err 4.480s 135.127us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.480s 135.127us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 14.550s 588.454us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 13.080s 1360.246us 20 20 100.00
lc_ctrl_sec_cm 8.750s 486.397us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 13.080s 1360.246us 20 20 100.00
lc_ctrl_sec_cm 8.750s 486.397us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 13.080s 1360.246us 20 20 100.00
lc_ctrl_sec_cm 8.750s 486.397us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 13.080s 1360.246us 20 20 100.00
lc_ctrl_sec_cm 8.750s 486.397us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 13.080s 1360.246us 20 20 100.00
lc_ctrl_sec_cm 8.750s 486.397us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 13.080s 1360.246us 20 20 100.00
lc_ctrl_sec_cm 8.750s 486.397us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 13.080s 1360.246us 20 20 100.00
lc_ctrl_sec_cm 8.750s 486.397us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 13.080s 1360.246us 20 20 100.00
lc_ctrl_sec_cm 8.750s 486.397us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 12.490s 387.656us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 10.580s 96.303us 20 20 100.00
lc_ctrl_jtag_state_post_trans 26.720s 1684.066us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 10.410s 888.535us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 10.410s 888.535us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 9.890s 547.008us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.920s 416.471us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.920s 416.471us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
lc_ctrl_stress_all_with_rand_reset 122.890s 4483.420us 2 10 20.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
lc_ctrl_stress_all_with_rand_reset 57238891153798906703891315437040403305278351630847291530920621072396269935331 174
UVM_INFO @ 1910010407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 101432895274569926445494306873289133383692689760553662564398430753409945875830 5714
UVM_INFO @ 1956624120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 47486926804999330076828398559905955247829845774993049729435553634800862767137 151
UVM_INFO @ 213501259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 61568348961629872648108849733115322186719636066632084335189833115681641672239 1884
UVM_INFO @ 3984033701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 70949452012730824471255705129486459812934060204419178725666393692176974941094 2211
UVM_INFO @ 16632658145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 22717906491874421651525412248103597447148881045733566767809842835653199873301 11272
UVM_INFO @ 12137493284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:923) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 2 test runs
lc_ctrl_stress_all_with_rand_reset 3143385592140450969514356098193872364703862676031860732435346310608221930223 8469
UVM_INFO @ 4369358625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 101442212069300603230661801075587424116931997830554916456201760495503023010178 1225
UVM_INFO @ 1686227419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 2 test runs
lc_ctrl_stress_all 36980549492748011259797119801402845938463137108738648612563086194440456989979 4655
UVM_INFO @ 3256304672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 82908730903115154164419543736118326574309072222487936431419226980285130324005 577
UVM_INFO @ 35653576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---