Simulation Results: otbn

 
04/07/2026 02:41:51 DVSim: v1.49.0 sha: 98a020b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.87 %
  • code
  • 81.49 %
  • assert
  • 88.50 %
  • func
  • 96.61 %
  • block
  • 97.81 %
  • line
  • 97.98 %
  • branch
  • 82.47 %
  • toggle
  • 82.13 %
  • FSM
  • 63.38 %
Validation stages
V1
100.00%
V2
98.16%
V2S
96.05%
V3
60.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 28.000s 43.728us 1 1 100.00
single_binary 100 100 100.00
otbn_single 96.000s 364.046us 100 100 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 38.000s 34.946us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 37.000s 42.230us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 42.000s 228.679us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 37.000s 17.326us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 38.000s 72.977us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 37.000s 42.230us 5 5 100.00
otbn_csr_aliasing 37.000s 17.326us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 90.000s 780.009us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 62.000s 328.524us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 65.000s 350.203us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 98.000s 611.013us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 130.000s 903.892us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 154.000s 666.405us 10 10 100.00
lc_escalation 57 60 95.00
otbn_escalate 38.000s 22.845us 57 60 95.00
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 7.000s 40.177us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 32.000s 160.599us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 38.000s 18.198us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 36.000s 49.906us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 9.000s 147.861us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 9.000s 147.861us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 38.000s 34.946us 1 1 100.00
otbn_csr_rw 37.000s 42.230us 5 5 100.00
otbn_csr_aliasing 37.000s 17.326us 1 1 100.00
otbn_same_csr_outstanding 31.000s 50.275us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 38.000s 34.946us 1 1 100.00
otbn_csr_rw 37.000s 42.230us 5 5 100.00
otbn_csr_aliasing 37.000s 17.326us 1 1 100.00
otbn_same_csr_outstanding 31.000s 50.275us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 40.000s 39.936us 10 10 100.00
otbn_dmem_err 38.000s 25.875us 15 15 100.00
internal_integrity 16 17 94.12
otbn_alu_bignum_mod_err 38.000s 54.310us 5 5 100.00
otbn_controller_ispr_rdata_err 40.000s 105.513us 5 5 100.00
otbn_mac_bignum_acc_err 41.000s 56.059us 4 5 80.00
otbn_urnd_err 9.000s 16.911us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 36.000s 20.663us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 40.000s 30.305us 2 2 100.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 35.000s 51.779us 9 10 90.00
tl_intg_err 25 30 83.33
otbn_sec_cm 56.000s 123.341us 0 5 0.00
otbn_tl_intg_err 45.000s 276.880us 25 25 100.00
passthru_mem_tl_intg_err 5 5 100.00
otbn_passthru_mem_tl_intg_err 91.000s 333.381us 5 5 100.00
prim_fsm_check 0 5 0.00
otbn_sec_cm 56.000s 123.341us 0 5 0.00
prim_count_check 0 5 0.00
otbn_sec_cm 56.000s 123.341us 0 5 0.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 28.000s 43.728us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 38.000s 25.875us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 40.000s 39.936us 10 10 100.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 45.000s 276.880us 25 25 100.00
sec_cm_controller_fsm_global_esc 57 60 95.00
otbn_escalate 38.000s 22.845us 57 60 95.00
sec_cm_controller_fsm_local_esc 35 40 87.50
otbn_imem_err 40.000s 39.936us 10 10 100.00
otbn_dmem_err 38.000s 25.875us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 40.177us 5 5 100.00
otbn_illegal_mem_acc 36.000s 20.663us 5 5 100.00
otbn_sec_cm 56.000s 123.341us 0 5 0.00
sec_cm_controller_fsm_sparse 0 5 0.00
otbn_sec_cm 56.000s 123.341us 0 5 0.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 96.000s 364.046us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 35 40 87.50
otbn_imem_err 40.000s 39.936us 10 10 100.00
otbn_dmem_err 38.000s 25.875us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 40.177us 5 5 100.00
otbn_illegal_mem_acc 36.000s 20.663us 5 5 100.00
otbn_sec_cm 56.000s 123.341us 0 5 0.00
sec_cm_scramble_ctrl_fsm_sparse 0 5 0.00
otbn_sec_cm 56.000s 123.341us 0 5 0.00
sec_cm_start_stop_ctrl_fsm_global_esc 57 60 95.00
otbn_escalate 38.000s 22.845us 57 60 95.00
sec_cm_start_stop_ctrl_fsm_local_esc 35 40 87.50
otbn_imem_err 40.000s 39.936us 10 10 100.00
otbn_dmem_err 38.000s 25.875us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 40.177us 5 5 100.00
otbn_illegal_mem_acc 36.000s 20.663us 5 5 100.00
otbn_sec_cm 56.000s 123.341us 0 5 0.00
sec_cm_start_stop_ctrl_fsm_sparse 0 5 0.00
otbn_sec_cm 56.000s 123.341us 0 5 0.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 96.000s 364.046us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 42.000s 35.992us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 38.000s 26.146us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 67.000s 429.314us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 67.000s 429.314us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 9 10 90.00
otbn_rf_base_intg_err 35.000s 44.796us 9 10 90.00
sec_cm_rf_base_data_reg_sw_glitch_detect 0 5 0.00
otbn_sec_cm 56.000s 123.341us 0 5 0.00
sec_cm_stack_wr_ptr_ctr_redun 0 5 0.00
otbn_sec_cm 56.000s 123.341us 0 5 0.00
sec_cm_rf_bignum_data_reg_sw_integrity 9 10 90.00
otbn_rf_bignum_intg_err 40.000s 56.611us 9 10 90.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 0 5 0.00
otbn_sec_cm 56.000s 123.341us 0 5 0.00
sec_cm_loop_stack_ctr_redun 0 5 0.00
otbn_sec_cm 56.000s 123.341us 0 5 0.00
sec_cm_loop_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 20.000s 49.456us 4 5 80.00
sec_cm_call_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 20.000s 49.456us 4 5 80.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 27.000s 27.445us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 96.000s 364.046us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 96.000s 364.046us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 96.000s 364.046us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 130.000s 903.892us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 96.000s 364.046us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 96.000s 364.046us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 25.000s 147.798us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 96.000s 364.046us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
otbn_sec_cm 56.000s 123.341us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 6 10 60.00
otbn_stress_all_with_rand_reset 529.000s 3509.101us 6 10 60.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 22.000s 40.372us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed 5 test runs
otbn_sec_cm 37980141469036333569565620753506408672697859840761176053592122726702284607825 130
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,211): (time 123341463 PS) Assertion tb.dut.u_otbn_core.gen_mai.u_otbn_mai.u_otbn_mask_accelerator.u_prim_fifo_sync_mask.gen_normal_fifo.depthShallNotExceedParamDepth has failed
UVM_ERROR @ 123341463 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 123341463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_cm 32769068659778658395738596552346758069815531802701981868308828092429423180117 102
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,211): (time 78418440 PS) Assertion tb.dut.u_otbn_core.gen_mai.u_otbn_mai.u_otbn_mask_accelerator.u_prim_fifo_sync_mask.gen_normal_fifo.depthShallNotExceedParamDepth has failed
UVM_ERROR @ 78418440 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 78418440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_cm 24099713864948301967768473001931646511923350689931608673868905734351007144658 119
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,211): (time 45469520 PS) Assertion tb.dut.u_otbn_core.gen_mai.u_otbn_mai.u_otbn_mask_accelerator.u_prim_fifo_sync_mask.gen_normal_fifo.depthShallNotExceedParamDepth has failed
UVM_ERROR @ 45469520 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 45469520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_cm 113590747052197668583006688630776658873683947494509707923147546075900020715271 106
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,211): (time 129780266 PS) Assertion tb.dut.u_otbn_core.gen_mai.u_otbn_mai.u_otbn_mask_accelerator.u_prim_fifo_sync_mask.gen_normal_fifo.depthShallNotExceedParamDepth has failed
UVM_ERROR @ 129780266 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 129780266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_cm 87160483060010830019717464188784984381800931346456088624675772443639911236507 96
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,211): (time 34145587 PS) Assertion tb.dut.u_otbn_core.gen_mai.u_otbn_mai.u_otbn_mask_accelerator.u_prim_fifo_sync_mask.gen_normal_fifo.depthShallNotExceedParamDepth has failed
UVM_ERROR @ 34145587 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 34145587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 3 test runs
otbn_mac_bignum_acc_err 76855620930018554860048374279738680744164241466503161723236767411319074676874 120
UVM_INFO @ 241370459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_bignum_intg_err 89542582581885792335184876444412277142224162597041863487296285004832209999 111
UVM_INFO @ 20969184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 102303132517706080330280106210622767891163795932414591943914172627682359626459 107
UVM_INFO @ 32224667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
otbn_stress_all_with_rand_reset 107403324990929714048435189520606198113052372929845811120928186071936845296525 236
UVM_INFO @ 3967839849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 91032601725894470460316795688754175957304667581350069804413987487390383276695 330
UVM_INFO @ 2360123089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 90784741278407627118478100715555349279622039889046534843870395407461411484656 169
UVM_INFO @ 1152274570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 2 test runs
otbn_stack_addr_integ_chk 66788996032093141225066006137039042765343639344429577757917330115358891799456 112
UVM_ERROR @ 25989031 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 25989031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 78883123242937961706699599307339723964754662799338930204892717076768826916092 120
UVM_ERROR @ 32737443 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 32737443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otbn_common_vseq] wait timeout occurred! 1 test run
otbn_stress_all_with_rand_reset 52106993937089065013752357573628005467812388308026837121875701072507315102408 167
UVM_INFO @ 10025412774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:217) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr otbn_reg_block.cmd (addr=*) 1 test run
otbn_rf_base_intg_err 28258948757734413798705865375346286643359298934448159987394560298541752954190 116
UVM_INFO @ 2029148552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,171): Assertion NotRunningWhenLocked_A has failed 1 test run
otbn_partial_wipe 103314860268154007512567061482628000018452442642697247754929220466227029226102 107
UVM_ERROR @ 23712569 ps: (otbn_idle_checker.sv:171) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 23712569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 1 test run
otbn_escalate 48798154730989544830606879256904932138164223098500325777332851356952001218882 125
UVM_INFO @ 1299574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---