Simulation Results: otp_ctrl

 
04/07/2026 02:41:51 DVSim: v1.49.0 sha: 98a020b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.47 %
  • code
  • 86.35 %
  • assert
  • 95.46 %
  • func
  • 92.59 %
  • line
  • 90.35 %
  • branch
  • 86.89 %
  • cond
  • 94.10 %
  • toggle
  • 95.81 %
  • FSM
  • 64.58 %
Validation stages
V1
92.31%
V2
96.81%
V2S
96.21%
V3
24.75%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.920s 53.387us 1 1 100.00
smoke 10 10 100.00
otp_ctrl_smoke 8.480s 1697.782us 10 10 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.340s 1081.519us 1 1 100.00
csr_rw 5 5 100.00
otp_ctrl_csr_rw 1.930s 146.093us 5 5 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 11.060s 2318.850us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.550s 92.213us 1 1 100.00
csr_mem_rw_with_rand_reset 3 5 60.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.340s 198.873us 3 5 60.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otp_ctrl_csr_rw 1.930s 146.093us 5 5 100.00
otp_ctrl_csr_aliasing 3.550s 92.213us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.460s 134.087us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.370s 556.813us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 13.620s 1401.681us 1 1 100.00
init_fail 300 300 100.00
otp_ctrl_init_fail 8.160s 3618.670us 300 300 100.00
partition_check 40 60 66.67
otp_ctrl_background_chks 55.990s 33735.065us 10 10 100.00
otp_ctrl_check_fail 61.640s 7990.090us 30 50 60.00
regwen_during_otp_init 30 30 100.00
otp_ctrl_regwen 10.870s 1369.925us 30 30 100.00
partition_lock 30 30 100.00
otp_ctrl_dai_lock 45.020s 31609.890us 30 30 100.00
interface_key_check 10 10 100.00
otp_ctrl_parallel_key_req 26.280s 2721.365us 10 10 100.00
lc_interactions 210 210 100.00
otp_ctrl_parallel_lc_req 27.960s 12265.952us 10 10 100.00
otp_ctrl_parallel_lc_esc 41.570s 26110.567us 200 200 100.00
otp_dai_errors 25 25 100.00
otp_ctrl_dai_errs 49.200s 21823.562us 25 25 100.00
otp_macro_errors 6 10 60.00
otp_ctrl_macro_errs 17.250s 1170.198us 6 10 60.00
test_access 10 10 100.00
otp_ctrl_test_access 40.760s 34082.046us 10 10 100.00
stress_all 10 10 100.00
otp_ctrl_stress_all 189.250s 19652.771us 10 10 100.00
intr_test 10 10 100.00
otp_ctrl_intr_test 1.980s 571.789us 10 10 100.00
alert_test 10 10 100.00
otp_ctrl_alert_test 3.450s 829.481us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otp_ctrl_tl_errors 7.250s 2130.616us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otp_ctrl_tl_errors 7.250s 2130.616us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.340s 1081.519us 1 1 100.00
otp_ctrl_csr_rw 1.930s 146.093us 5 5 100.00
otp_ctrl_csr_aliasing 3.550s 92.213us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.420s 158.855us 5 5 100.00
tl_d_partial_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.340s 1081.519us 1 1 100.00
otp_ctrl_csr_rw 1.930s 146.093us 5 5 100.00
otp_ctrl_csr_aliasing 3.550s 92.213us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.420s 158.855us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
tl_intg_err 29 30 96.67
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
otp_ctrl_tl_intg_err 72.710s 11875.342us 24 25 96.00
prim_count_check 5 5 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
prim_fsm_check 5 5 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
sec_cm_bus_integrity 24 25 96.00
otp_ctrl_tl_intg_err 72.710s 11875.342us 24 25 96.00
sec_cm_secret_mem_scramble 10 10 100.00
otp_ctrl_smoke 8.480s 1697.782us 10 10 100.00
sec_cm_part_mem_digest 10 10 100.00
otp_ctrl_smoke 8.480s 1697.782us 10 10 100.00
sec_cm_dai_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
sec_cm_kdi_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
sec_cm_lci_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
sec_cm_part_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
sec_cm_scrmbl_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
sec_cm_timer_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
sec_cm_dai_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
sec_cm_kdi_seed_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
sec_cm_kdi_entropy_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
sec_cm_lci_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
sec_cm_part_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
sec_cm_scrmbl_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
sec_cm_timer_integ_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
sec_cm_timer_cnsty_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
sec_cm_timer_lfsr_redun 5 5 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
sec_cm_dai_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 41.570s 26110.567us 200 200 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
sec_cm_lci_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 41.570s 26110.567us 200 200 100.00
sec_cm_kdi_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 41.570s 26110.567us 200 200 100.00
sec_cm_part_fsm_local_esc 206 210 98.10
otp_ctrl_parallel_lc_esc 41.570s 26110.567us 200 200 100.00
otp_ctrl_macro_errs 17.250s 1170.198us 6 10 60.00
sec_cm_scrmbl_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 41.570s 26110.567us 200 200 100.00
sec_cm_timer_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 41.570s 26110.567us 200 200 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
sec_cm_dai_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 41.570s 26110.567us 200 200 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
sec_cm_lci_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 41.570s 26110.567us 200 200 100.00
sec_cm_kdi_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 41.570s 26110.567us 200 200 100.00
sec_cm_part_fsm_global_esc 206 210 98.10
otp_ctrl_parallel_lc_esc 41.570s 26110.567us 200 200 100.00
otp_ctrl_macro_errs 17.250s 1170.198us 6 10 60.00
sec_cm_scrmbl_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 41.570s 26110.567us 200 200 100.00
sec_cm_timer_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 41.570s 26110.567us 200 200 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
sec_cm_part_data_reg_integrity 300 300 100.00
otp_ctrl_init_fail 8.160s 3618.670us 300 300 100.00
sec_cm_part_data_reg_bkgn_chk 30 50 60.00
otp_ctrl_check_fail 61.640s 7990.090us 30 50 60.00
sec_cm_part_mem_regren 30 30 100.00
otp_ctrl_dai_lock 45.020s 31609.890us 30 30 100.00
sec_cm_part_mem_sw_unreadable 30 30 100.00
otp_ctrl_dai_lock 45.020s 31609.890us 30 30 100.00
sec_cm_part_mem_sw_unwritable 30 30 100.00
otp_ctrl_dai_lock 45.020s 31609.890us 30 30 100.00
sec_cm_lc_part_mem_sw_noaccess 30 30 100.00
otp_ctrl_dai_lock 45.020s 31609.890us 30 30 100.00
sec_cm_access_ctrl_mubi 30 30 100.00
otp_ctrl_dai_lock 45.020s 31609.890us 30 30 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
otp_ctrl_smoke 8.480s 1697.782us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 30 30 100.00
otp_ctrl_dai_lock 45.020s 31609.890us 30 30 100.00
sec_cm_test_bus_lc_gated 10 10 100.00
otp_ctrl_smoke 8.480s 1697.782us 10 10 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 327.060s 176057.498us 5 5 100.00
sec_cm_direct_access_config_regwen 30 30 100.00
otp_ctrl_regwen 10.870s 1369.925us 30 30 100.00
sec_cm_check_trigger_config_regwen 10 10 100.00
otp_ctrl_smoke 8.480s 1697.782us 10 10 100.00
sec_cm_check_config_regwen 10 10 100.00
otp_ctrl_smoke 8.480s 1697.782us 10 10 100.00
sec_cm_macro_mem_integrity 6 10 60.00
otp_ctrl_macro_errs 17.250s 1170.198us 6 10 60.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 7.830s 3629.019us 1 1 100.00
stress_all_with_rand_reset 24 100 24.00
otp_ctrl_stress_all_with_rand_reset 3600.109s 0.000us 24 100 24.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 42 test runs
otp_ctrl_check_fail 14990026919676481037485787433850894056847177666919422043248023204213377222469 597
UVM_INFO @ 74751331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 21740124942810259635156520682160058042291191965391262136586855811727874910041 27995
UVM_INFO @ 17595060171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 92856128456750222839504888072240537303086783613331376307555223556891007399066 3500
UVM_INFO @ 2394879000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 28703969380481062801051165826746597431802357094344459263885337470619662169810 541
UVM_INFO @ 158463482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 68667887904850219283178152174338752621698729278070519148888811942503020167090 19229
UVM_INFO @ 1817676133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 74407261968952749771274581302939320993307396751919157657111122322885244314 3603
UVM_INFO @ 7953743056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 37219457452984046513994914104158963442391842114030141657212016482343681646348 10207
UVM_INFO @ 483393199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 62644277316033413227699784888707176812717034999288866482699379273555453157459 5487
UVM_INFO @ 1497848188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 72718970925534308564125607208301736654248946257266842447534538205477315262717 10937
UVM_INFO @ 8015868129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4790738040901663802091875626498323921785665602482180034558093705695738802781 247
UVM_INFO @ 1530757051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 112177129276265287791843015217158774641147237627834701910638217109111624184140 485
UVM_INFO @ 1593671965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 31617842433287439280959082052141234983040085658293032980517056947878651735837 4546
UVM_INFO @ 137037296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 31627096209590243198744718143743355833496285247899234969946811577873696565428 4278
UVM_INFO @ 673275692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114525706113890256366896474331482797004900264209447312477382645877853772897397 147
UVM_INFO @ 33149572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 23396051721648597326091538101964737807248633257199093442739896178943941788551 4075
UVM_INFO @ 6632192779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 43117140654329110188888426480670809806155266196165346284098040415912175761362 5743
UVM_INFO @ 2618164277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 101836276102744601052216470810403533718370901122332276665421586915878216190362 1633
UVM_INFO @ 2004706643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 58718700617139116493121340952656198615013967157774566970002924796896001543049 811
UVM_INFO @ 295187932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 85248723411961983155275321471352046671882544150949403649768812505585275168401 177
UVM_INFO @ 568498069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 16154709192229659480458487363983983077295395061578299668873293011771809927040 17249
UVM_INFO @ 2247399025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 85973416833219109163601094020243382440010543174904470521951636707342172186710 445
UVM_INFO @ 142631672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 9767693630568038773620088917354548282658021234090619752126124797310888674665 2322
UVM_INFO @ 466560612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 78562984834865877596816750190911626362859056806915594839408960577719630468516 1733
UVM_INFO @ 474902499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 106501222002124140409883136312949515657333021466442976161257612877776911250018 37488
UVM_INFO @ 1046336669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 10973086343162727866933073257620485442639386600470780358189244492378553253324 4557
UVM_INFO @ 3865521746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 25098927333153229763467350808114946766751439912175229484410818915104194023136 23670
UVM_INFO @ 16052321925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 6308200626549877029940145035118644969643065275732820279730984568030701567366 3491
UVM_INFO @ 572485476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 73254354301846934018661088761378113726237746926317328529765559810178949706816 6141
UVM_INFO @ 2371528473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 104321295526084868151641511659807061979008232732179373558058605798362348451808 4730
UVM_INFO @ 545411659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 63384265243978025987555366745240954020666216311095249296711647375753478956052 5930
UVM_INFO @ 11072213522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 31095488663418004537873576771423136331402521599058624347243453854358941060507 4225
UVM_INFO @ 1770296170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 78113139879751544464340184149394000271948772218058446255180049596477656547578 3747
UVM_INFO @ 34029285752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 58415964301308716861043905116713500757319107002366236172860599278619082589009 1129
UVM_INFO @ 1289063988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 97063021044319852932326755867748397644342894179678245096877110651067337753671 1656
UVM_INFO @ 211676520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 63699591142650509789671736874544249629966287868649540050076190711010955299255 6707
UVM_INFO @ 1778791926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 78613076585222936813514460701128949339736967306175780051660783754253314420947 4440
UVM_INFO @ 793370690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 26130033208206276164048189186706144073012543373035897348829174033675655106847 7965
UVM_INFO @ 187119628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18384528254729066012029649317545744730715849193297780050296645664024285287410 159
UVM_INFO @ 50466387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 62921956769828541310465177610820394003490663945441847369585407006311231900424 12454
UVM_INFO @ 4152677318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 82820923649932356296610606062000995199490236516547851858963025818440585726566 15320
UVM_INFO @ 828571670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 39313717993691653699427203379241651704719812765621353859466673391329065416131 391
UVM_INFO @ 94641261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 26632010816166023772937895760034796363992480072400896509108888479491568413353 4787
UVM_INFO @ 1090153587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 22 test runs
otp_ctrl_stress_all_with_rand_reset 88180459181505781582300727944284186961206821801810292122484774524325722492870 28298
UVM_INFO @ 35072974750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 79494853395582802119784037263773134613731978352760393239195503511980052261628 4011
UVM_INFO @ 15075337427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 74379798585415029387985012170170562000931457673810557324850141558573556103474 6980
UVM_INFO @ 716584724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2687267485966713944318135962653825831673794160730527061508992088616325717537 31933
UVM_INFO @ 14500630414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 3330974600805217464341677804846723292093836816693011659175702195968026704598 26526
UVM_INFO @ 17635296699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 12346155193228478720293452387796131579365698560235859399019361725728517749375 2338
UVM_INFO @ 16895045433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45522762120971406703817453224412404699186887667363975061219704977758066537315 92
UVM_INFO @ 62289439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45718720742403302899561852779588590772531501397181548221185483665571405822235 93
UVM_INFO @ 28348997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 86547521329774288083243106816425032450644159033299959720013793024332460763804 5359
UVM_INFO @ 1301772321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 107522160734382182248658777229948205155270648274984418773962620668992252380518 93
UVM_INFO @ 54663890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 65759247065976112853644172184718973780173513232688470021526350994711356474507 92
UVM_INFO @ 29380261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 7974838863467562246456046508797757044075962904881478573274430831237951901350 93
UVM_INFO @ 29062083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 97632991819099411313301145293610780794532870846151953699784050765334055654809 31012
UVM_INFO @ 2712710881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 62479525452840711751430860173658932220561256386832569976331236874097411540816 5011
UVM_INFO @ 1066627597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 56102848968558472021276515409592740029182851518836273371901618722081348898685 93
UVM_INFO @ 36449789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80261357776910812551276351496705633818117990127565762971210244784278689535902 8567
UVM_INFO @ 724392023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 111743862753287883990617201077581455792581716799770986395527744612605619712296 92
UVM_INFO @ 27858601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 74307885776279232660769632779782056740982845917706439143129964819193953580299 138
UVM_INFO @ 277974395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42002926525861245233005593626383061831904675801302009679075919591345488884439 93
UVM_INFO @ 117568860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 106766456838149622068995684805982566002873524803459776029056950053768902190039 19198
UVM_INFO @ 3620587544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 65111438312061161805861997900689767746845952468073009783759350217421448105395 5526
UVM_INFO @ 719024842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 60397989486794529536938781854080227572417543772788433029289670252238130879730 92
UVM_INFO @ 27811840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 21 test runs
otp_ctrl_stress_all_with_rand_reset 19880437191131664853727928590818272080901860941072565299292626142285700652035 24386
UVM_INFO @ 21091998947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 101451721939437274510551577514909546533256449507141624730493964706090751538720 11229
UVM_INFO @ 2257448702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 10972115208299549213229784831906175776441880551933094218842659208080022964030 1368
UVM_INFO @ 4702530820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 11946184951530498075098754741828336216755401181874548090247436960374043427978 6953
UVM_INFO @ 26614092514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2914295732630500992032550977167130462414823541552127171425607157123874058867 9171
UVM_INFO @ 4050097923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 54206801841168501085276904724080193811854777296715829540841768151045946282471 4246
UVM_INFO @ 2179360671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 66174958748634805997054573994958294711375559798151262390581356499312591795975 230
UVM_INFO @ 270224924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 55966778573514695102455409881505459761839794899468674707747536610511488084319 109
UVM_INFO @ 71256657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45477674819766723715741782126368629502213543662987417130413940651482641151765 485
UVM_INFO @ 335024992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 107055999285858416397781954470935132990614178282225926795336920462152996322925 4116
UVM_INFO @ 568868303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 14024202462195039194177241756477862024127993074214274224408729630028108401529 437
UVM_INFO @ 1601372920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 37134683532582038957729256957299269335468085877087585030752707585331386311250 1548
UVM_INFO @ 1368963703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 66567308662497357199409420366062423784796671870746538130581520161860944766320 3792
UVM_INFO @ 1271467437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 1065077855760053264602006372490052004542075331600321761664329276277472636989 22595
UVM_INFO @ 8108192058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 103994351177760232941367657914563787972425379581981792416580110433220630306494 10024
UVM_INFO @ 4169472722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 51236688519207516834615229450668688380948371472619681827705831007759925395636 13770
UVM_INFO @ 3289494281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 72494387536090923940505859004730434425996783019904954481163264151510482626737 583
UVM_INFO @ 309549409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42364662878891497366479192965143405809662341942584534086231211606722800723294 3917
UVM_INFO @ 1250076450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 33505843206510511137478441427453960857233783668646638347193602613055828076822 8034
UVM_INFO @ 1500755144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 24374461751116251113420177042905392342992671145623214849814489200560519755504 7917
UVM_INFO @ 2962113754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 47538283761831282371267179566742958218818262464100218637270353331209244020868 15007
UVM_INFO @ 2072835591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
otp_ctrl_stress_all_with_rand_reset 96983513141271088353710239749221984053611956491093903739810234032532584553993 2607
UVM_INFO @ 2007451208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 5791310081784820604098051217992372796781809429116392310283859419400394156808 13056
UVM_INFO @ 20544091747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 113250064675754910372366913257363695145290492281025883325493347014697198641028 30419
UVM_INFO @ 90426923208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 113748069371228527211954626254479199628597689350557183451800580356684806928437 11726
UVM_INFO @ 16237903850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 28332574331276195373251007406964367326773847697372742586569022450279754211269 8135
UVM_INFO @ 10911137381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 106132307338895058063671371224760498662494489429802791948398391047367376084101 6281
UVM_INFO @ 12253694627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 5 test runs
otp_ctrl_csr_mem_rw_with_rand_reset 5589925026572067025287095289820277532038052916538259538032248110900734087429 92
UVM_INFO @ 26083948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 48755892564580014105787517682082855806620156133850618298610460829586046103874 92
UVM_INFO @ 35802278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80644436866124539199996276968062713396394385703840604056940700965399996711875 2951
UVM_INFO @ 12941048882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 62690149819843024876949917435539934723425649096400663671573960279229434225329 1538
UVM_INFO @ 274371226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 110275897567403748902422951747583789317808428507948009364493670308128246296986 92
UVM_INFO @ 426913791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen 2 test runs
otp_ctrl_stress_all_with_rand_reset 110241230993971372506617671126198020442937021550439079551366776129192320469344 4153
UVM_INFO @ 934968783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 62672660362750576536068190569805103657224331283732660780507907631632273630622 287
UVM_INFO @ 293229049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(cio_test_en_o == *)' 1 test run
otp_ctrl_csr_mem_rw_with_rand_reset 90961894080748619471331733435413684586072054548775209746132911344270661525738 93
UVM_ERROR @ 27061028 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 27061028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=80) 1 test run
otp_ctrl_stress_all_with_rand_reset 109348305050038291611598019398514277606690263213579803542286682251219137090444 13249
UVM_INFO @ 20716193360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_common_vseq] wait timeout occurred! 1 test run
otp_ctrl_tl_intg_err 36960191794551346829122981669243956311579997702134016855791138391774350281185 211
UVM_INFO @ 11875341568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
otp_ctrl_stress_all_with_rand_reset 14759482737335353752507475960396777922064876026473468346688007407254966427942 None
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 14986607127401674781865348926530860774617400133134776219638519901062387866641 94
UVM_INFO @ 4310358110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---