Simulation Results

Simulation Results: pwrmgr

04/07/2026 02:41:51 DVSim: v1.49.0 sha: 98a020b json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
98.50 %

code
97.54 %

assert
98.96 %

func
99.01 %

line
99.09 %

branch
96.37 %

cond
96.61 %

toggle
99.62 %

FSM
96.00 %

Validation stages

V1		100.00%
V2		97.08%
V2S		100.00%
V3		80.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	pwrmgr_smoke	0.810s	26.174us	10	10	100.00
csr_hw_reset				1	1	100.00
	pwrmgr_csr_hw_reset	0.770s	49.028us	1	1	100.00
csr_rw				5	5	100.00
	pwrmgr_csr_rw	0.870s	17.721us	5	5	100.00
csr_bit_bash				1	1	100.00
	pwrmgr_csr_bit_bash	2.550s	646.029us	1	1	100.00
csr_aliasing				1	1	100.00
	pwrmgr_csr_aliasing	1.020s	327.340us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	pwrmgr_csr_mem_rw_with_rand_reset	1.060s	196.950us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	pwrmgr_csr_rw	0.870s	17.721us	5	5	100.00
	pwrmgr_csr_aliasing	1.020s	327.340us	1	1	100.00

133/137 passed

97.08 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wakeup				10	10	100.00
	pwrmgr_wakeup	1.190s	234.052us	10	10	100.00
control_clks				10	10	100.00
	pwrmgr_wakeup	1.190s	234.052us	10	10	100.00
aborted_low_power				20	20	100.00
	pwrmgr_aborted_low_power	0.940s	51.497us	10	10	100.00
	pwrmgr_lowpower_invalid	0.830s	47.005us	10	10	100.00
reset				19	20	95.00
	pwrmgr_reset	0.870s	83.501us	10	10	100.00
	pwrmgr_reset_invalid	1.120s	98.092us	9	10	90.00
main_power_glitch_reset				10	10	100.00
	pwrmgr_reset	0.870s	83.501us	10	10	100.00
reset_wakeup_race				10	10	100.00
	pwrmgr_wakeup_reset	1.300s	365.252us	10	10	100.00
lowpower_wakeup_race				10	10	100.00
	pwrmgr_lowpower_wakeup_race	0.980s	264.056us	10	10	100.00
disable_rom_integrity_check				9	10	90.00
	pwrmgr_disable_rom_integrity_check	2.270s	1000.000us	9	10	90.00
stress_all				8	10	80.00
	pwrmgr_stress_all	25.440s	10126.501us	8	10	80.00
intr_test				10	10	100.00
	pwrmgr_intr_test	0.780s	29.741us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	pwrmgr_tl_errors	2.050s	49.576us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	pwrmgr_tl_errors	2.050s	49.576us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	pwrmgr_csr_hw_reset	0.770s	49.028us	1	1	100.00
	pwrmgr_csr_rw	0.870s	17.721us	5	5	100.00
	pwrmgr_csr_aliasing	1.020s	327.340us	1	1	100.00
	pwrmgr_same_csr_outstanding	1.000s	76.912us	5	5	100.00
tl_d_partial_access				12	12	100.00
	pwrmgr_csr_hw_reset	0.770s	49.028us	1	1	100.00
	pwrmgr_csr_rw	0.870s	17.721us	5	5	100.00
	pwrmgr_csr_aliasing	1.020s	327.340us	1	1	100.00
	pwrmgr_same_csr_outstanding	1.000s	76.912us	5	5	100.00

V2S

115/115 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	pwrmgr_tl_intg_err	1.640s	195.267us	25	25	100.00
	pwrmgr_sec_cm	1.680s	645.527us	5	5	100.00
prim_count_check				5	5	100.00
	pwrmgr_sec_cm	1.680s	645.527us	5	5	100.00
prim_fsm_check				5	5	100.00
	pwrmgr_sec_cm	1.680s	645.527us	5	5	100.00
sec_cm_bus_integrity				25	25	100.00
	pwrmgr_tl_intg_err	1.640s	195.267us	25	25	100.00
sec_cm_lc_ctrl_intersig_mubi				10	10	100.00
	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	2.170s	838.465us	10	10	100.00
sec_cm_rom_ctrl_intersig_mubi				20	20	100.00
	pwrmgr_wakeup_reset	1.300s	365.252us	10	10	100.00
	pwrmgr_repeat_wakeup_reset	2.340s	1332.278us	10	10	100.00
sec_cm_rstmgr_intersig_mubi				10	10	100.00
	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.980s	75.079us	10	10	100.00
sec_cm_esc_rx_clk_bkgn_chk				10	10	100.00
	pwrmgr_esc_clk_rst_malfunc	0.820s	31.508us	10	10	100.00
sec_cm_esc_rx_clk_local_esc				5	5	100.00
	pwrmgr_sec_cm	1.680s	645.527us	5	5	100.00
sec_cm_fsm_sparse				5	5	100.00
	pwrmgr_sec_cm	1.680s	645.527us	5	5	100.00
sec_cm_fsm_terminal				5	5	100.00
	pwrmgr_sec_cm	1.680s	645.527us	5	5	100.00
sec_cm_ctrl_flow_global_esc				10	10	100.00
	pwrmgr_global_esc	0.820s	47.308us	10	10	100.00
sec_cm_main_pd_rst_local_esc				10	10	100.00
	pwrmgr_glitch	0.750s	31.904us	10	10	100.00
sec_cm_ctrl_config_regwen				10	10	100.00
	pwrmgr_sec_cm_ctrl_config_regwen	1.280s	236.978us	10	10	100.00
sec_cm_wakeup_config_regwen				5	5	100.00
	pwrmgr_csr_rw	0.870s	17.721us	5	5	100.00
sec_cm_reset_config_regwen				5	5	100.00
	pwrmgr_csr_rw	0.870s	17.721us	5	5	100.00

16/20 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
escalation_timeout				6	10	60.00
	pwrmgr_escalation_timeout	0.900s	374.081us	6	10	60.00
stress_all_with_rand_reset				10	10	100.00
	pwrmgr_stress_all_with_rand_reset	13.850s	16400.321us	10	10	100.00

Error Messages

	Test	seed	line	log context
Offending '((!clk_en) \|\| status)'				4 test runs
	pwrmgr_escalation_timeout	104677772190964904963682218461634195626493388778943515412896245639366559635981	79	UVM_ERROR @ 404527279 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A UVM_INFO @ 404527279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	pwrmgr_escalation_timeout	27203895325392148450894785616763007840488045232768353909613680023126168148389	79	UVM_ERROR @ 186568660 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A UVM_INFO @ 186568660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	pwrmgr_escalation_timeout	47871304289150221095414033230755883838682626940428541846222799730979069461364	79	UVM_ERROR @ 98712791 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A UVM_INFO @ 98712791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	pwrmgr_escalation_timeout	115087131604542333717864128195522112760456157456076483572423333071358942438487	79	UVM_ERROR @ 369127400 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A UVM_INFO @ 369127400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred!				2 test runs
	pwrmgr_stress_all	71822885087132549163752743180805679323477038376872836560474247997973070270783	441	UVM_INFO @ 11262046381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	pwrmgr_stress_all	45798579783316810920721696491892113588961693763274386912429463293610942351962	234	UVM_INFO @ 10126501152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	pwrmgr_disable_rom_integrity_check	111572009419981683106198490261064678715177533607882027618582789848131566539770	142	UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitOtpInit				1 test run
	pwrmgr_reset_invalid	75815861916340213189709739920209853466242266619933318671893057380275371099394	85	UVM_INFO @ 198585001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---