Simulation Results: rom_ctrl/32kb

 
04/07/2026 02:41:51 DVSim: v1.49.0 sha: 98a020b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.54 %
  • code
  • 98.68 %
  • assert
  • 96.95 %
  • func
  • 100.00 %
  • line
  • 99.46 %
  • branch
  • 100.00 %
  • cond
  • 98.37 %
  • toggle
  • 95.57 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
94.92%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 4.460s 1982.849us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.280s 355.073us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 5.510s 168.944us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.730s 475.415us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.600s 539.066us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.840s 172.260us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 5.510s 168.944us 5 5 100.00
rom_ctrl_csr_aliasing 3.600s 539.066us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.720s 170.914us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.270s 477.303us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 4.160s 87.329us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 26.030s 1549.683us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 8.960s 309.215us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 5.820s 554.792us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 12.060s 211.962us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 12.060s 211.962us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 4.280s 355.073us 1 1 100.00
rom_ctrl_csr_rw 5.510s 168.944us 5 5 100.00
rom_ctrl_csr_aliasing 3.600s 539.066us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.800s 496.230us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 4.280s 355.073us 1 1 100.00
rom_ctrl_csr_rw 5.510s 168.944us 5 5 100.00
rom_ctrl_csr_aliasing 3.600s 539.066us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.800s 496.230us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 121.490s 43125.185us 17 20 85.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 28.420s 2293.895us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 276.490s 741.106us 5 5 100.00
rom_ctrl_tl_intg_err 64.020s 279.796us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 276.490s 741.106us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 276.490s 741.106us 5 5 100.00
sec_cm_checker_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 121.490s 43125.185us 17 20 85.00
sec_cm_checker_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 121.490s 43125.185us 17 20 85.00
sec_cm_checker_fsm_local_esc 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 121.490s 43125.185us 17 20 85.00
sec_cm_compare_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 121.490s 43125.185us 17 20 85.00
sec_cm_compare_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 121.490s 43125.185us 17 20 85.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 276.490s 741.106us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 276.490s 741.106us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 4.460s 1982.849us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 4.460s 1982.849us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 4.460s 1982.849us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 64.020s 279.796us 25 25 100.00
sec_cm_bus_local_esc 19 22 86.36
rom_ctrl_corrupt_sig_fatal_chk 121.490s 43125.185us 17 20 85.00
rom_ctrl_kmac_err_chk 8.960s 309.215us 2 2 100.00
sec_cm_mux_mubi 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 121.490s 43125.185us 17 20 85.00
sec_cm_mux_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 121.490s 43125.185us 17 20 85.00
sec_cm_ctrl_redun 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 121.490s 43125.185us 17 20 85.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 28.420s 2293.895us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 276.490s 741.106us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 18 20 90.00
rom_ctrl_stress_all_with_rand_reset 357.110s 16565.508us 18 20 90.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 3 test runs
rom_ctrl_corrupt_sig_fatal_chk 69936686351919176546731074908929869654442304366498767161763808111518361617531 84
UVM_INFO @ 6294048110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 66604944275406068020091292609682737150898501646789291188385346039499180389666 104
UVM_INFO @ 5285694433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 42514990979814092287516124168259501689259452614758522885156301142544939685621 101
UVM_INFO @ 4087704538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 104883142842065628550720092426285598417829006054340247777117630247247434991159 79
UVM_INFO @ 87328621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 93303917152416921277615741422159183622022765445749490278678719796582548068019 79
UVM_INFO @ 497823880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:235) [scoreboard] Check failed item.d_data[i**+:*] == exp_data[i**+:*] (* [*] vs * [*]) TLUL ROM read data incorrect 2 test runs
rom_ctrl_stress_all_with_rand_reset 88164434440695062319314177910552714997216779737669171108783486852538917927466 159
UVM_INFO @ 1960806021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 73642626443974743171789493329601738206842464735673329565110171402674446591863 156
UVM_INFO @ 4857171174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---