Simulation Results: rom_ctrl/64kb

 
04/07/2026 02:41:51 DVSim: v1.49.0 sha: 98a020b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.47 %
  • code
  • 98.68 %
  • assert
  • 97.68 %
  • func
  • 99.05 %
  • line
  • 99.46 %
  • branch
  • 100.00 %
  • cond
  • 98.37 %
  • toggle
  • 95.57 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
100.00%
V3
95.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 12.420s 4305.264us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 12.480s 736.704us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 10.230s 205.421us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 12.700s 287.503us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.840s 216.106us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 10.380s 1125.715us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 10.230s 205.421us 5 5 100.00
rom_ctrl_csr_aliasing 7.840s 216.106us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.150s 1021.925us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.760s 673.139us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 10.420s 251.982us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 51.210s 8855.906us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 18.980s 903.083us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 11.140s 391.856us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 14.830s 866.682us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 14.830s 866.682us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 12.480s 736.704us 1 1 100.00
rom_ctrl_csr_rw 10.230s 205.421us 5 5 100.00
rom_ctrl_csr_aliasing 7.840s 216.106us 1 1 100.00
rom_ctrl_same_csr_outstanding 14.260s 1201.330us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 12.480s 736.704us 1 1 100.00
rom_ctrl_csr_rw 10.230s 205.421us 5 5 100.00
rom_ctrl_csr_aliasing 7.840s 216.106us 1 1 100.00
rom_ctrl_same_csr_outstanding 14.260s 1201.330us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 240.410s 12268.432us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 59.940s 1588.019us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 625.270s 2247.289us 5 5 100.00
rom_ctrl_tl_intg_err 135.610s 4738.152us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 625.270s 2247.289us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 625.270s 2247.289us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 240.410s 12268.432us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 240.410s 12268.432us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 240.410s 12268.432us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 240.410s 12268.432us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 240.410s 12268.432us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 625.270s 2247.289us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 625.270s 2247.289us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 12.420s 4305.264us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 12.420s 4305.264us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 12.420s 4305.264us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 135.610s 4738.152us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 240.410s 12268.432us 20 20 100.00
rom_ctrl_kmac_err_chk 18.980s 903.083us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 240.410s 12268.432us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 240.410s 12268.432us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 240.410s 12268.432us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 59.940s 1588.019us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 625.270s 2247.289us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 19 20 95.00
rom_ctrl_stress_all_with_rand_reset 441.560s 25274.044us 19 20 95.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 73837460320628025013430105101343318578095019954511195861469628715213779435420 79
UVM_INFO @ 330472381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 63754688014783821199430735938845912783943884565882719089296269305642777497403 79
UVM_INFO @ 251981518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [rom_ctrl_common_vseq] wait timeout occurred! 1 test run
rom_ctrl_stress_all_with_rand_reset 12605597146446084410063905719097248916840054134521065557507623973472590535549 109
UVM_INFO @ 13741044582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---