| V1 |
|
100.00% |
| V2 |
|
85.83% |
| V2S |
|
100.00% |
| V3 |
|
35.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 2.320s | 625.673us | 20 | 20 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.870s | 12.933us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| rv_timer_csr_rw | 0.860s | 12.786us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_timer_csr_bit_bash | 1.850s | 182.400us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_timer_csr_aliasing | 1.110s | 30.503us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.100s | 45.547us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| rv_timer_csr_rw | 0.860s | 12.786us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.110s | 30.503us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 2 | 20 | 10.00 | |||
| rv_timer_random_reset | 7.930s | 9491.035us | 2 | 20 | 10.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 2.440s | 2905.619us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 570.020s | 2818106.802us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 570.020s | 2818106.802us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 12.230s | 7581.610us | 20 | 20 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| rv_timer_alert_test | 0.840s | 14.086us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| rv_timer_intr_test | 0.850s | 35.579us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 3.040s | 684.651us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 3.040s | 684.651us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.870s | 12.933us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.860s | 12.786us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.110s | 30.503us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.960s | 137.230us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.870s | 12.933us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.860s | 12.786us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.110s | 30.503us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.960s | 137.230us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| rv_timer_sec_cm | 0.990s | 318.450us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.600s | 135.568us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| rv_timer_tl_intg_err | 1.600s | 135.568us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 2 | 10 | 20.00 | |||
| rv_timer_min | 2.340s | 2027.544us | 2 | 10 | 20.00 | |
| max_value | 0 | 10 | 0.00 | |||
| rv_timer_max | 1.310s | 894.575us | 0 | 10 | 0.00 | |
| stress_all_with_rand_reset | 12 | 20 | 60.00 | |||
| rv_timer_stress_all_with_rand_reset | 62.660s | 69716.541us | 12 | 20 | 60.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | 26 test runs | |||
| rv_timer_min | 80341754779927826764096758175477603252969694236684460127835791701515378878458 | 75 |
UVM_INFO @ 61685683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 102196727425521793276511681345956593605702870003629115553344239444087637624248 | 76 |
UVM_INFO @ 656633742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 3143645134054838229991887245127593443375758206389967996348906002647012298826 | 77 |
UVM_INFO @ 800457819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 111241483341221220643214607983233823067852987459251191599773320292310467350543 | 75 |
UVM_INFO @ 280911026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 23806954480204586116324218156202532088844958016424513484047325339670578154123 | 76 |
UVM_INFO @ 937173070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 112971318172493266012674669452598681146713109999659190821359239403237063690162 | 75 |
UVM_INFO @ 2027543535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 96089975267822696826068138012478985886739310816367022547878411330221736395267 | 75 |
UVM_INFO @ 604915317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 91637437697951567847457430659711413442305692297802000260064413414172411951063 | 76 |
UVM_INFO @ 822903755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 90146813200657045949389345330778768389596621406144325692431088354973640885655 | 76 |
UVM_INFO @ 9491035047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 115342705991374204399964785597548304122229406147476073695379178258112955218436 | 75 |
UVM_INFO @ 245750261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 85645878653456096268398920112847505236283044429348444144042775303460757071269 | 75 |
UVM_INFO @ 70770447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 52339623060802879328399943919033222048225255957781023344462607732711866737547 | 75 |
UVM_INFO @ 63613738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 32072229080311974260031354702936754566478479593635883832006408336543197840797 | 76 |
UVM_INFO @ 143519675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 102070247228580330448621847426287481777754363665450186537917488738910088737629 | 77 |
UVM_INFO @ 223210388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 32817455127792846711677328971638877299005921627269678229616696068898748280554 | 75 |
UVM_INFO @ 526308638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 74993600464248956148458175944471942641963550795163350710238375771148808514063 | 76 |
UVM_INFO @ 354405461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 42419119136937537077770548230810268267163899852414252769570887931021972624287 | 75 |
UVM_INFO @ 9140580781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 51882984988751798964973590658881481578147239218219991164308594873338407359185 | 75 |
UVM_INFO @ 146780791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 3779976219978081268946316755272488707541126520689265486564314369250026271422 | 76 |
UVM_INFO @ 107409475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 106628328574402210090002686134912516005746169895825462113567577799405637575793 | 75 |
UVM_INFO @ 430587486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 23678129041451185263273448262114537171224197086437720051581408741175349064096 | 75 |
UVM_INFO @ 389444548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 115240144259274761423393484191874267459080265117556180159163092538196885624673 | 75 |
UVM_INFO @ 1328238680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 56016951410322501580532772665262145542849257558072284416863063729975750008592 | 75 |
UVM_INFO @ 26791728465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 99534958322136789430615049386496422016637727715564280052061387465168219450676 | 75 |
UVM_INFO @ 1007428623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 63712804195750002005415111191951160268093250449779424348358585482421584644664 | 75 |
UVM_INFO @ 511956822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 55432891922855730118890241734429203807944879735455205491661198673066252617695 | 76 |
UVM_INFO @ 1880886035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 10 test runs | |||
| rv_timer_max | 97263638769543107236551675482028504198715598808189365744544874532688979882129 | 76 |
UVM_INFO @ 208988606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 47904102292142710703838076142864459148455866604572817429129766547548175055119 | 76 |
UVM_INFO @ 183207264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 84673064134597795614181065865910593029455664977517280170139113732185197886658 | 75 |
UVM_INFO @ 385916469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 71032575460229721794378655143835314666213704647059353891081014782384948093778 | 76 |
UVM_INFO @ 894575267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 104894253634238754190313349194681432683117413709339663448787512640215554654705 | 75 |
UVM_INFO @ 87998474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 103279643731863926391403188461341088422463779926800181904317378454387019509233 | 75 |
UVM_INFO @ 85621139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 84967621155872448498115103495413383188815425038868742868930969203074075299710 | 75 |
UVM_INFO @ 180938772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 112533568081236163443844570411813934283895182430424903965207841124961869900767 | 75 |
UVM_INFO @ 46938281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 7174706950402786953999431455589310940533035348141978759052565507939128258942 | 75 |
UVM_INFO @ 43197003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 101798398460573443390563742595985329399039432436047699908469092633971002320281 | 75 |
UVM_INFO @ 167719661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) | 6 test runs | |||
| rv_timer_stress_all_with_rand_reset | 10681740885494435707739873386186728912988629116868465211624934598673484590896 | 88 |
UVM_INFO @ 342920051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 60180971493919558823108521674828067569569451830170855255278851524693202953932 | 196 |
UVM_INFO @ 9356672893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 24012852373335803280862440385906536451079317028664825356394530939307117283814 | 109 |
UVM_INFO @ 225981988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 70305718739173955722181705747243681807228505516462881514979225708294241446283 | 92 |
UVM_INFO @ 455371724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 89931868660689894224466123966787194091615365862963969717255318897244031806348 | 112 |
UVM_INFO @ 2771932568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 29177573403073346354727724928856085317659311586052253789293570516148090920774 | 182 |
UVM_INFO @ 2287636461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | 2 test runs | |||
| rv_timer_stress_all_with_rand_reset | 12140632517127339728767459076046102177791204928142514459673895946413795113675 | 202 |
UVM_INFO @ 5416207299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 82842772907805909079402262617372505346357465524000239102983591568516300517938 | 281 |
UVM_INFO @ 3148778061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|